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參數(shù)資料
| 型號： | MC68HC705V8 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 2/28頁 |
| 文件大小： | 220K |
| 代理商： | MC68HC705V8 |
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MOTOROLA
2
AN1224/D
performed on a bit-by-bit basis whenever multiple nodes begin to transmit simultaneously. J1850 allows for
the use of a single or dual wire bus, two data rates (10.4 kbps or 41.7 kbps), and two bit encoding
techniques (pulse width modulation (PWM) or variable pulse width modulation (VPW)).
Features
A J1850 message, or frame, consists of a start of frame (SOF) delimiter, a one- or three-byte header, zero
to eight data bytes, a cyclical redundancy check (CRC) byte, an end of data (EOD) delimiter, and an
optional in-frame response byte, followed by an end of frame (EOF) delimiter. Frames using a single-byte
header are transmitted at 10.4 kbps, using VPW modulation, and contain a CRC byte for error detection
(see Figure 1a). Frames using a one-byte consolidated header or a three-byte consolidated header can be
transmitted at either 41.7 kbps or 10.4 kbps, using either PWM or VPW modulation techniques, and also
contain a CRC byte for error detection (see Figures 1b and 1c).
Figure 1a. Single-Byte Header Frame Format
Figure 1b. One-Byte Consolidated Header Frame Format
Figure 1c. Three-byte Consolidated Header Frame Format
Each frame can contain up to 12 bytes (VPW) or 101 bit times (PWM), with each byte transmitted MSB
first. The optional in-frame response can contain either a single byte or multiple bytes, with or without a
CRC byte. Table 1 summarizes the allowable features of the J1850 protocol. The requirements of each
individual network determine which features are used.
DATA 1
DATA N
CRC
IFR
EOD
EOF
HEADER
IDLE
BUS
SOF
IDLE
BUS
DATA 1
DATA N
CRC
IFR
EOD
EOF
HEADER
IDLE
BUS
SOF
IDLE
BUS
PRI/TYPE
TARGET ID
SOURCE ID
DATA 1
DATA N
CRC
IFR
EOD
IDLE
BUS
EOF
SOF
IDLE
BUS
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