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參數資料
型號: MPC603E7TEC
廠商: Motorola, Inc.
英文描述: PowerPC 603e RISC Microprocessor
中文描述: RISC微處理器的PowerPC 603e
文件頁數: 6/36頁
文件大小: 551K
代理商: MPC603E7TEC
6
PID7t-603e Hardware Specifications
Electrical and Thermal Characteristics
Table 4 provides the package thermal characteristics for the PID7t-603e.
Table 5 provides the DC electrical characteristics for the PID7t-603e.
Table 4. Package Thermal Characteristics
Characteristic
Symbol
Value
CBGA
Value
PBGA
Rating
Package die junction-to-case thermal resistance (typical)
q
JC
0.095
8.0
°C/W
Package die junction-to-ball thermal resistance (typical)
q
JB
3.5
13
°C/W
Note:
Refer to Section 1.8, “System Design Information,” for more details about thermal management.
Table 5. DC Electrical Specifications
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0
Tj
105 °C
Characteristic
Symbol
Min
Max
Unit
Notes
Input high voltage (all inputs except SYSCLK)
V
IH
2.0
5.5
V
Input low voltage (all inputs except SYSCLK)
V
IL
GND
0.8
V
SYSCLK input high voltage
CV
IH
2.4
5.5
V
SYSCLK input low voltage
CV
IL
GND
0.4
V
Input leakage current, V
in
= 3.465 V
I
in
30
μA
1,2
V
in
= 5.5 V
I
in
300
μA
1,2
Hi-Z (off-state) leakage current, V
in
= 3.465 V
I
TSI
30
μA
1,2
V
in
= 5.5 V
I
TSI
300
μA
1,2
Output high voltage, I
OH
= D7
mA
V
OH
2.4
V
Output low voltage, I
OL
= 7
mA
V
OL
0.4
V
Capacitance, V
ARTRY)
in
= 0 V, f = 1 MHz (excludes TS, ABB, DBB, and
C
in
10.0
pF
3
Capacitance, V
in
= 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY) C
in
15.0
pF
3
Notes
:
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. The leakage is measured for nominal OVdd and Vdd or both OVdd and Vdd must vary in the same direction
(for example, both OVdd and Vdd vary by either +5% or -5%).
3. Capacitance is periodically sampled rather than 100% tested.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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