
MPC9446
TIMING SOLUTIONS
5
MOTOROLA
Table 8: DC CHARACTERISTICS
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 2.5V
±
5%, T
A
= --40
°
C to +85
°
C)
Symbol
Characteristics
V
IH
Input High Voltage
V
IL
Input Low Voltage
V
OH
Output High Voltage
V
OL
Output Low Voltage
Z
OUT
Output Impedance
I
IN
I
CCQc
Maximum Quiescent Supply Current
a. The MPC9446 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated transmission
line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
series terminated transmission lines per output.
b. Input pull-up / pull-down resistors influence input current.
c. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Min
1.7
-0.3
1.8
Typ
Max
Unit
V
V
V
V
μ
A
mA
Condition
V
CC
+ 0.3
0.7
LVCMOS
LVCMOS
I
OH
=-15 mA
a
I
OL
= 15 mA
0.6
17 - 20
b
Input Current
b
±
200
2.0
V
IN
=GND or V
IN
=VCC
All V
CC
Pins
Table 9: AC CHARACTERISTICS
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 2.5V
±
5%, T
A
= --40
°
C to +85
°
C)
a b
Symbol
Characteristics
f
ref
Input Frequency
f
MAX
Maximum Output Frequency
Min
0
0
0
1.4
Typ
Max
250
c
250
b
125
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ps
ps
ps
Condition
÷
1 output
÷
2 output
FSELx=0
FSELx=1
t
P, REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ, HZ
t
PZL, LZ
t
sk(O)
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
1.0
d
5.6
5.5
10
10
150
200
350
0.7 to 1.7V
CCLK0,1 to any Q
CCLK0,1 to any Q
2.6
2.6
Output Disable Time
Output Enable Time
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
t
sk(PP)
t
SK(P)
Device-to-device Skew
Output pulse skew
e
3.0
200
ns
ps
DC
Q
t
r
, t
f
Output Duty Cycle
÷
1 or
÷
2 output
45
50
55
%
DC
REF
= 50%
0.6 to 1.8V
Output Rise/Fall Time
0.1
1.0
ns
a. AC characteristics apply for parallel output termination of 50
to V
TT
.
b. AC specifications are design targets, final specification is pending device characterization.
c. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e. Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
- t
pHL
|.
Table 10: AC CHARACTERISTICS
(V
CC
= 3.3V + 5%, V
CCA
, V
CCB
, V
CCC
= 2.5V + 5% or 3.3V + 5%,
T
A
= --40
°
C to +85
°
C)
a b
Symbol
Characteristics
t
sk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
Min
Typ
Max
150
250
350
Unit
ps
ps
ps
Condition
t
sk(PP)
t
PLH,HL
t
SK(P)
Device-to-device Skew
Propagation delay
Output pulse skew
c
2.5
ns
CCLK0,1 to any Q
See 3.3V table
DC
Q
Output Duty Cycle
÷
1 or
÷
2 output
45
50
250
55
ps
%
DC
REF
= 50%
a. AC characteristics apply for parallel output termination of 50
to V
TT
.
b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
c. Output pulse skew is the absolute difference of the propagation delay times: | t
pLH
- t
pHL
|.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.