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參數資料
| 型號： | MPC9600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| 中文描述： | 低電壓2.5 V和3.3 V的CMOS PLL時鐘驅動器 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 321K |
| 代理商： | MPC9600 |
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9600/D
Rev. 2, 11/2001
Motorola, Inc. 2001
!
The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL
based clock driver and fanout buffer. With output frequencies up to 200
MHz and output skews of 150 ps, the device meets the needs of the most
demanding clock tree applications.
Features:
Multiplication of input frequency by 2, 3, 4 and 6
Distribution of output frequency to 21 outputs organized in three output
banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable
Fully integrated PLL
Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz
Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz
LVCMOS outputs
Outputs disable to high impedance (except QFB)
LVCMOS or LVPECL reference clock options
48 lead QFP packaging
±
50 ps cycle-to-cycle jitter
150 ps maximum output-to-output skew
200 ps maximum static phase offset window
The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock
driver. The MPC9600 has the capability to generate clock signals of 50 to
200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is
optimized for this frequency range and does not require external loop filter
components. QFB provides an output for the external feedback path to
the feedback input FB_IN. The QFB divider ratio is configurable and
determines the PLL frequency multiplication factor when QFB is directly
connected to FB_IN. The MPC9600 is optimized for minimizing the
propagation delay between the clock input and FB_IN.
Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining
the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6.
The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use
LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels.
The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50
transmission to VTT=VCC/2.
For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With
guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements
of the most demanding systems.
The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the
reference clock will bypass the PLL.
The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.
3.3 V OR 2.5 V
LOW VOLTAGE CMOS
PLL CLOCK DRIVER
FA SUFFIX
48–LEAD LQFP PACKAGE
CASE 932–03
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關代理商/技術參數 |
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| MPC9600AE | 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9600AER2 | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9600FA | 功能描述:IC CLOCK DRVR PLL LV 1:21 48LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC9608 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1:10 LVCMOS Zero Delay Clock Buffer |
| MPC9608AC | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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