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參數(shù)資料
| 型號： | MPC9600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| 中文描述： | 低電壓2.5 V和3.3 V的CMOS PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 321K |
| 代理商： | MPC9600 |
MOTOROLA
TIMING SOLUTIONS
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC
÷
2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9600 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 8. “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9600 clock driver is effectively doubled
due to its capability to drive multiple lines.
Figure 8. Single versus Dual Transmission Lines
The waveform plots in Figure 9. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9600 output buffer is more than
sufficient to drive 50
transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43 ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9600. The output waveform in Figure 9. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0
÷
(RS+R0 +Z0))
14
IN
MPC9600
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC9600
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
Z0 = 50
|| 50
RS = 36
|| 36
R0 = 14
VL = 3.0 ( 25
÷
(18+17+25)
= 1.31 V
At the load end the voltage will double due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).
Figure 9. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 10. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
TIME (nS)
V
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Figure 10. Optimized Dual Line Termination
14
MPC9600
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22
22
= 50
50
25
= 25
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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