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參數資料
| 型號： | MPC9600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| 中文描述： | 低電壓2.5 V和3.3 V的CMOS PLL時鐘驅動器 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 321K |
| 代理商： | MPC9600 |
TIMING SOLUTIONS
MOTOROLA
Table 4: DC CHARACTERISTICS
(VCC = 2.5 V
±
5%, TA = –40
°
to +85
°
C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
VIL
VPP
VCMRa
VOH
VOL
ZOUT
IIN
ICCA
ICCQ
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. The MPC9600 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50
parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50
series terminated transmission lines per
output.
Input High Voltage
1.7
VCC + 0.3
0.7
V
LVCMOS
Input Low Voltage
V
LVCMOS
Peak-to-peak input voltage (DC)
PCLK, PCLK
250
mV
LVPECL
Common Mode Range (DC)
PCLK, PCLK
1.0
VCC-0.6
V
LVPECL
IOH=-15 mAb
IOL= 15 mA
Output High Voltage
1.8
V
Output Low Voltage
0.6
V
Output Impedance
17 – 20
Input Leakage Current
±
150
μ
A
VIN = VCC or GND
VCCA Pin
All VCC Pins
Maximum PLL Supply Current
3.0
5.0
mA
Maximum Quiescent Supply Current
1.0
mA
Table 5: AC CHARACTERISTICS
(VCC = 3.3 V
±
5% or VCC = 2.5 V
±
5%, TA = –40
°
to +85
°
C)
a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
8 feedback (FSEL_FB=0)
12 feedback (FSEL_FB=1)
Static test mode (VCCA = GND)
25
16.67
0
50
33
500
MHz
MHz
MHz
PLL locked
PLL locked
VCCA = GND
fVCO
fMAX
VCO Frequency
200
400
MHz
Maximum Output Frequency
2 outputs (FSELx=0)
4 outputs (FSELx=1)
100
50
200
100
MHz
MHz
PLL locked
PLL locked
frefDC
VPP
VCMRb
Reference Input Duty Cycle
25
75
%
Peak-to-peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
Common Mode Range
PCLK, PCLK (VCC = 3.3 V
±
5%)
PCLK, PCLK (VCC = 2.5 V
±
5%)
1.2
1.2
VCC-0.8
VCC-0.6
V
V
LVPECL
LVPECL
tr, tf
t(
)
CCLK Input Rise/Fall Time
1.0
ns
see Figure 12
Propagation Delay (static phase offset)
CCLK to FB_IN
PECL_CLK to FB_IN
–60
+30
+40
+130
+140
+230
ps
ps
PLL locked
PLL locked
tsk(o)
Output-to-output Skew
all outputs, single frequency
all outputs, multiple frequency
within QAx output bank
within QBx outputs
within QCx outputs
70
70
30
40
30
150
150
75
125
75
ps
ps
ps
ps
ps
Measured at
coincident
rising edge
DC
Output Duty Cycle
45
50
55
%
tr, tf
tPLZ, HZ
tPZL, ZH
BW
Output Rise/Fall Time
0.1
1.0
ns
see Figure 12
Output Disable Time
10
ns
Output Enable Time
10
ns
PLL Closed Loop Bandwidth
8 feedback (FSEL_FB=0)
12 feedback (FSEL_FB=1)
1.0 – 10
0.6 – 4.0
MHz
MHz
–3 dB point of
PLL transfer
characteristic
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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