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參數資料
| 型號： | MPC9600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| 中文描述： | 低電壓2.5 V和3.3 V的CMOS PLL時鐘驅動器 |
| 文件頁數： | 7/16頁 |
| 文件大小： | 321K |
| 代理商： | MPC9600 |
TIMING SOLUTIONS
MOTOROLA
APPLICATIONS INFORMATION
Programming the MPC9600
The MPC9600 clock driver outputs can be configured into
several divider modes. Additionally the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The selectable feedback
divider of the three output groups allows the user to configure
the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency
ratios. The use of even dividers ensure that the output duty
cycle is always 50%. Table 6 illustrates the various output
Table 6: Output Frequency Relationshipa for QFB connected to FB_IN
configurations, the table describes the outputs using the
input clock frequency CLK as a reference.
The feedback divider division settings establish the output
relationship, in addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 50 MHz to 200
MHz while the VCO frequency range is specified from 200
MHz to 400 MHz and should not be exceeded for stable
operation.
Configuration Inputs
Input
Frequency
Range CLK
[MHz]
Output Frequency Ratio and Range
FSEL_FB
FSELA
FSELB
FSELC
Ratio, QAx [MHz]
Ratio, QBx [MHz]
Ratio, QCx [MHz]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4 CLK (100–200)
4 CLK (100–200)
4 CLK (100–200)
4 CLK (100–200)
2 CLK (50.0–100)
2 CLK (50.0–100)
2 CLK (50.0–100)
2 CLK (50.0–100)
6 CLK (100–200)
6 CLK (100–200)
6 CLK (100–200)
6 CLK (100–200)
3 CLK (50.0–100)
3 CLK (50.0–100)
3 CLK (50.0–100)
3 CLK (50.0–100)
4 CLK (100–200)
4 CLK (100–200)
2 CLK (50.0–100)
2 CLK (50.0–100)
4 CLK (100–200)
4 CLK (100–200)
2 CLK (50.0–100)
2 CLK (50.0–100)
6 CLK (100–200)
6 CLK (100–200)
3 CLK (50.0–100)
3 CLK (50.0–100)
6 CLK (100–200)
6 CLK (100–200)
3 CLK (50.0–100)
3 CLK (50.0–100)
4 CLK (100–200)
2 CLK (50.0–100)
4 CLK (100–200)
2 CLK (50.0–100)
4 CLK (100–200)
2 CLK (50.0–100)
4 CLK (100–200)
2 CLK (50.0–100)
6 CLK (100–200)
3 CLK (50.0–100)
6 CLK (100–200)
3 CLK (50.0–100)
6 CLK (100–200)
3 CLK (50.0–100)
6 CLK (100–200)
3 CLK (50.0–100)
25.0–50.0
16.67–33.33
a. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400.
Typical and Maximum Period Jitter Specification
Device Configuration
QA0 to QA6
QB0 to QB6
QC0 to QC6
Typ
Max
Typ
Max
Typ
Max
All output banks in
2 or
4 divider configurationa
2 (FSELA=0 and FESLB=0 and FSELC=0)
4 (FSELA=1 and FESLB=1 and FSELC=1)
4 divider configurationsb
for output banks in
2 divider configurations
for output banks in
4 divider configurations
25
20
50
70
50
50
70
100
25
20
50
70
Mixed
2/
80
25
130
70
100
60
150
100
80
25
130
70
a. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 1 for an example configuration.
b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. See Figure 2 for an example.
Typical and Maximum Cycle–to–cycle Jitter Specification
Device Configuration
QA0 to QA6
QB0 to QB6
QC0 to QC6
Typ
Max
Typ
Max
Typ
Max
All output banks in
2 or
4 divider configurationa
2 (FSELA=0 and FESLB=0 and FSELC=0)
4 (FSELA=1 and FESLB=1 and FSELC=1)
4 divider configurationsb
for output banks in
2 divider configurations
for output banks in
4 divider configurations
40
40
90
110
80
120
130
180
40
40
90
110
Mixed
2/
150
30
250
110
200
120
280
180
150
30
250
110
a. In this configuration, all MPC9600 outputs generate the same clock frequency.
b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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