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參數資料
| 型號： | MPC9893 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
| 中文描述： | 低壓智能動態時鐘鎖相環（IDC機房）開關 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 475K |
| 代理商： | MPC9893 |
MPC9893
MOTOROLA
TIMING SOLUTIONS
The waveform plots in Figure 9. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9893 output buffer is more than
sufficient to drive 50
transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9893. The output waveform in Figure 9. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
V
L
= V
S
( Z
0
÷
(R
S
+R
0
+Z
0
))
Z
0
= 50
|| 50
R
S
= 36
|| 36
R
0
= 14
V
L
= 3.0 ( 25
÷
(18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
Figure 9. Single versus Dual Waveforms
TIME (nS)
V
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 10. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallelcombination is added
to the output buffer impedance the line impedance is perfectly
matched.
Figure 10. Optimized Dual Line Termination
14
MPC9893
OUTPUT
BUFFER
R
S
= 22
Z
O
= 50
R
S
= 22
Z
O
= 50
14
+ 22
k
22
= 50
k
50
25
= 25
Figure 11. CLK0, CLK1 MPC9893 AC test reference for V
cc
= 3.3V and V
cc
= 2.5V
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9893 DUT
V
TT
V
TT
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC9893AE | 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893AER2 | 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893FA | 功能描述:時鐘發生器及支持產品 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 48-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9893FAR2 - Tape and Reel |
| MPC9894 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Input Redundant IDCS Clock Generator |
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