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參數資料
型號: MPC9893
廠商: Motorola, Inc.
英文描述: Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch
中文描述: 低壓智能動態時鐘鎖相環(IDC機房)開關
文件頁數: 9/16頁
文件大小: 475K
代理商: MPC9893
MPC9893
TIMING SOLUTIONS
MOTOROLA
feedback divider result in lower I/O jitter than the jitter limits in
the AC characterisitics (table 8 on page 6). When calculating
the part--to--part skew, Table 11 “Internal VCO frequency
fVCO”
should be used to determine the actual VCO
frequency, then use Figure 5 “Max. I/O Phase Jitter versus
VCO Frequency” to determine the maximum I/O jitter for the
specific VCO frequency and divider configuration. In above
example calculation, the internal VCO frequency of 400 MHz
corresponds to a maximum I/O jitter of 30 ps (RMS).
Table 11: Internal VCO frequency f
VCO
MPC9893
Configuration
fVCO
PLL feedback
divider FB
M1H, M12H, M2H, M22H
M3, M32
4 * f
ref
6 * f
ref
8 * f
ref
4
6
M1M, M12M, M2M,
M22M, M4, M42
8
M1L, M12L, M8, M82
16 * f
ref
16
Figure 5. Max. I/O Phase Jitter versus VCO Frequency
The cycle--to--cycle jitter and period jitter of the MPC9893
depend on the output configuration and on the frequency of
the internal VCO. Using the outputs of bank A and bank B at
the same frequency (FSEL3=0) results in a lower jitter than
the split output frequency configuration (FSEL3=1). The jitter
also decreases with an increasing internal VCO frequency.
Figures 4 to 6 represent the maximum jitter of the MPC9893.
Figure 6. Max. Cycle--to--Cycle Jitter versus VCO
Frequency
Figure 7. Max. Period Jitter versus VCO Frequency
Driving Transmission Lines
The MPC9893 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to V
CC
÷
2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9893 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 8. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9893 clock driver is effectively doubled due to its
capability to drive multiple lines.
Figure 8. Single versus Dual Transmission Lines
14
IN
MPC9893
OUTPUT
BUFFER
R
S
= 36
Z
O
= 50
OutA
14
IN
MPC9893
OUTPUT
BUFFER
R
S
= 36
Z
O
= 50
OutB0
R
S
= 36
Z
O
= 50
OutB1
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關代理商/技術參數
參數描述
MPC9893AE 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9893AER2 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9893FA 功能描述:時鐘發生器及支持產品 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
MPC9893FAR2 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 48-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9893FAR2 - Tape and Reel
MPC9894 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Input Redundant IDCS Clock Generator
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