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參數資料
| 型號： | MPC9893 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
| 中文描述： | 低壓智能動態時鐘鎖相環（IDC機房）開關 |
| 文件頁數： | 6/16頁 |
| 文件大小： | 475K |
| 代理商： | MPC9893 |
MPC9893
MOTOROLA
TIMING SOLUTIONS
Table 8: AC CHARACTERISTICS
(V
CC
= 3.3V
±
5% or V
CC
= 2.5V
±
5%, T
A
= --40
°
to 85
°
C)
a
Symbol
Characteristics
f
ref
Input Frequency
Min
15.0
30.0
40.0
30.0
60.0
15.0
30.0
60.0
Typ
Max
25.0
50.0
66.6
50.0
100.0
12.5
50.0
100.0
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Condition
PLL locked
FSEL= 000x
FSEL= 001x
FSEL= 010x
FSEL= 011x
FSEL= 100x
FSEL= 101x
FSEL= 110x
FSEL= 111x
f
MAX
Maximum Output Frequency
FSEL= 000x
FSEL= 001x
FSEL= 010x
FSEL= 011x
FSEL= 100x
FSEL= 101x
FSEL= 110x
FSEL= 111x
60.0
60.0
60.0
30.0
60.0
7.5
15.0
30.0
40
200.0
200.0
200.0
100.0
200.0
25.0
50.0
100.0
60
1.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
PLL locked
f
refDC
tr, tf
t
(
)
Reference Input Duty Cycle
CLK0, 1 Input Rise/Fall Time
Propagation Delay (static phase offset, CLKx to FB)
V
CC
=3.3V
±
5% and FSEL[0:2]=111
0.8 to 2.0V
PLL locked
V
CC
=3.3V
±
5%
V
CC
=2.5V
±
5% and FSEL[0:2]=111
V
CC
=2.5V
±
5%
--60
-200
-125
-400
+50
+100
+25
+100
ps
ps
ps
ps
t
Rate of period change (phase slew rate)
QAx outputs
QBx outputs (FSEL=xxx0)
QBx outputs (FSEL=xxx1)
Output-to-output Skew
b
150
150
300
50
100
125
55
1.0
10
10
225
425
ps/cycle
Failover
switch
t
sk(O)
(within bank)
(bank-to-bank)
(any output to QFB)
ps
ps
ps
%
ns
ns
ns
ps
ps
DC
O
t
r
, t
f
t
PLZ, HZ
t
PZL, LZ
t
JIT(CC)
Output duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
c
45
0.1
50
0.55 to 2.4V
FSEL3=0
FSEL3=1
See
applications
section
See
applications
section
See
applications
section
t
JIT(PER)
Period Jitter
c
FSEL3=0
FSEL3=1
150
250
ps
ps
t
JIT(
)
I/O Phase Jitter
d
FB=4: FSEL[0:2]=100 or 111
FB=6: FSEL[0:2]=010
FB=8: FSEL[0:2]=001, 011, or 110
FB=16: FSEL[0:2]=000 or 101
PLL closed loop bandwidth
e
Maximum PLL Lock Time
AC characteristics apply for parallel output termination of 50
to V
TT
.
See application section for part-to-part skew calculation.
Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section on page 9.
I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See application section on page 8 and 9 for more
information and for the calculation for other confidence factors than 1
σ.
-3dB point of PLL transfer characteristics.
RMS (1
σ
)
RMS (1
σ
)
RMS (1
σ
)
RMS (1
σ
)
FSEL=111x
40
50
55
70
ps
ps
ps
ps
MHz
ms
BW
t
LOCK
0.8-4.0
10
a.
b.
c.
d.
e.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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