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參數(shù)資料
| 型號： | NCP1381DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Low−Standby High Performance PWM Controller |
| 中文描述： | 1 A SWITCHING CONTROLLER, 125 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大小： | 559K |
| 代理商： | NCP1381DR2G |
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NCP1381
http://onsemi.com
4
MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
supply
Maximum Power Supply Voltage on Pin 10 (V
CC
), Pin 9 (DRV), and Pin 11 (GTS)
20
V
Maximum Current in Pin 10 (V
CC
)
30
mA
Maximum Current in Pin 11 (GTS)
20
mA
Maximum Current in Pin 9 (DRV)
1
A
Power Supply Voltage on all Other Pins Except Pin 10 (V
CC
), Pin 9 (DRV), Pin 3 (DMG) and
Pin 11 (GTS)
0.3 to 5
V
Maximum Current Into All Other Pins Except Pin 10 (V
CC
), Pin 9 (DRV) and Pin 11 (GTS)
10
mA
I
dem
Maximum Current in Pin 3 (DMG), When 10 V ESD Zener is Activated
+3 / 3
mA
R
JA
Thermal Resistance JunctiontoAir, SO14
150
°
C/W
TJ
MAX
Maximum Junction Temperature
150
°
C
Storage Temperature Range
60 to +150
°
C
ESD Capability, Human Body Model per MILSTD883, Method 3015 (All Pins Except Ref)
2
kV
ESD Capability, Human Body Model per MILSTD883, Method 3015 (Ref Pin)
1.8
kV
ESD Capability, Machine Model
200
V
NOTE:
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78.
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25
°
C, for min/max values T
J
= 0
°
C to +125
°
C, V
CC
= 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION
VCC
ON
Turnon Threshold Level, V
CC
Going Up
10
13
15
17.9
V
VCC
OFF
Minimum Operating Voltage After Turnon
10
9
10
11
V
VCC
latch
V
CC
Decreasing Level at Which the Latchoff Phase Ends
10
7
V
VCC
reset
V
CC
Level at Which the Internal Logic Gets Reset
10
4
V
I
startup
Startup Current (V
CC
< VCC
ON
)
10
2
15
A
I
CC1
Internal IC Consumption, No Output Load on Pin 9, F
SW
= 60 kHz
10
1.4
1.8
mA
I
CC2
Internal IC Consumption, 1 nF Output Load on Pin 9, F
SW
= 60 kHz
10
2.1
2.6
mA
I
CC3
Internal IC Consumption, Latchoff Phase
10
1.4
mA
DRIVE OUTPUT
T
r
Output Voltage RiseTime @ C
L
= 1 nF, 1090% of Output Signal
9
15
ns
T
f
Output Voltage FallTime @ C
L
= 1 nF, 1090% of Output Signal
9
15
ns
R
OH
Source Resistance
9
9
R
OL
Sink Resistance
9
8
CURRENT COMPARATOR
I
IB
Input Bias Current @ 1 V Input Level on Pin 7
7
0.02
A
I
Limit
Maximum Internal Current Setpoint at V
BO
= 0
7
0.75
0.8
0.85
V
G
m
Transconductance Amplifier Offsetting CS at V
BO
= 2 V
7
70
85
100
S
T
DELCS
Propagation Delay from CS Detected to Gate Turned off (Pin 9 Loaded
by 1 nF)
7
90
ns
T
LEB
Leading Edge Blanking Duration
7
300
370
ns
S
Start
Typical Internal Softstart Period at Startup
2.5
4.0
6.0
ms
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