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參數資料
| 型號： | NCP1381DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩壓器 |
| 英文描述： | Low−Standby High Performance PWM Controller |
| 中文描述： | 1 A SWITCHING CONTROLLER, 125 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁數： | 9/26頁 |
| 文件大小： | 559K |
| 代理商： | NCP1381DR2G |
NCP1381
http://onsemi.com
9
Figure 6.
V
CC
DRV
VCC
ON
VCC
OFF
100 ms
< 100 ms
Bunch Length Given by Timer
Bunch Length Given
by VCC
OFF
If V
CC
drops below VCC
OFF
during a portion where the timer
counts, pulses are immediately stopped and the latchoff phase
is entered. Here, in this example, the timer was set to 100 ms.
QuasiResonance Operation
QuasiResonance (QR) implies that the controller
permanently monitors the transformer core flux activity and
ensures Borderline Conduction Mode (BCM) operation.
That is to say, when the switch closes, the current ramps up
in the magnetizing inductance L
P
until it reaches a setpoint
imposed by the feedback loop. At this point, the power
switch opens and the energy transfers from the primary side
to the secondary (isolated) portion. The secondary diode is
now biased and the output voltage “flies back” to the
primary side, now demagnetizing the primary inductance
L
P
. When this current reaches zero, the transformer core is
said to be “reset” ( = 0). At this time, we can turn the
MOSFET on again to create a new cycle. Figure 7
and 8
portray the typical waveforms with their associated
captions. If a delay TW is introduced further to the core reset
detection and before biasing the power MOSFET, the drain
signal Vds(t) has the time to go through a minimum, also
called valley. Therefore, when we will finally reactivate the
power MOSFET, its draintosource voltage will be
minimum, reducing capacitive losses but also its
gatecharge value, since the Miller effect gets diminished at
low Vds.
Figure 7. Typical QuasiResonance
Waveform
TW
t
OFF
Leakage
Ringing
1st Valley
t
ON
Figure 8. Magnetizing Inductance Current
Waveforms
s
OFF
N
(V
out
V
f
)
L
P
s
ON
V
in
L
P
I
peak
ON
OFF
0
I
P
= 0
TW
The flux activity monitoring is actually made via an
auxiliary winding, obeying the law, V
aux
= N . d / dt.
Figure 9 describes how the detection is made, since the
signal obtained on the auxiliary winding is centered to zero.
Let’s split the events with their associated circuitry:
t
ON
The D flipflop output is high, the MOSFET is enhanced
and current growsup in the primary winding. This is the
on
portion of Figure 8, left side of the triangle. When the driver
output went high, its rising edge triggered a 8 s timer. This
8 s timer provides a true frequency clamp by driving the
Dinput of the flipflop. Now, when the peak current
reaches the level imposed by the feedback loop, a reset
occurs and the flipflop output comes low.
If for any reason the controller keeps the gate high
(DRV
out
) implying a t
ON
longer than 50 s, then all pulses
are stopped and the controller enters a safe, autorecovery,
restart mode. This condition can occur if the current sense
pin does not receive any signal from the sense resistor or if
a shortcircuit brings the CS pin to ground for instance.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| NCP1382DR2G | 功能描述:電流型 PWM 控制器 L-STNDBY PWM CNTRLR RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| NCP1392B | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:High-Voltage Half-Bridge Driver with Inbuilt Oscillator |
| NCP1392B_09 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:High-Voltage Half-Bridge Driver with Inbuiltc Oscillator |
| NCP1392BDR2G | 功能描述:功率驅動器IC HV HALF-BRIDGE DRVER RoHS:否 制造商:Micrel 產品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| NCP1392DDR2G | 功能描述:功率驅動器IC HV HALF-BRIDGE DRIVER RoHS:否 制造商:Micrel 產品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
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