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參數資料
| 型號： | P87LPC760 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP |
| 中文描述： | 低功耗，低價格，低引腳數（14針），1字節檢察官辦公室微控制器 |
| 文件頁數： | 11/56頁 |
| 文件大小： | 290K |
| 代理商： | P87LPC760 |
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Philips Semiconductors
Preliminary data
P87LPC760
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2002 Mar 07
8
FUNCTIONAL DESCRIPTION
Details of P87LPC760 functions will be described in the following
sections.
Enhanced CPU
The P87LPC760 uses an enhanced 80C51 CPU which runs at twice
the speed of standard 80C51 devices. This means that the
performance of the P87LPC760 running at 5 MHz is exactly the
same as that of a standard 80C51 running at 10 MHz. A machine
cycle consists of 6 oscillator cycles, and most instructions execute in
6 or 12 clocks. A user configurable option allows restoring standard
80C51 execution timing. In that case, a machine cycle becomes 12
oscillator cycles.
In the following sections, the term “CPU clock” is used to refer to the
clock that controls internal instruction execution. This may
sometimes be different from the externally applied clock, as in the
case where the part is configured for standard 80C51 timing by
means of the CLKR configuration bit or in the case where the clock
is divided down via the setting of the DIVM register. These features
are described in the Oscillator section.
Analog Functions
The P87LPC760 incorporates one Analog Comparator. In order to
give the best analog function performance and to minimize power
consumption, pins that are actually being used for analog functions
must have the digital outputs and the digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input
Only (high impedance) mode as described in the I/O Ports section.
Digital inputs on port 0 may be disabled through the use of the
PT0AD register. Each bit in this register corresponds to one pin of
Port 0. Setting the corresponding bit in PT0AD disables that pin’s
digital input. Port bits that have their digital inputs disabled will be
read as 0 by any instruction that accesses the port.
Analog Comparators
An analog comparator is provided on the P87LPC760. Input and
output options allow use of the comparator in a number of different
configurations. Comparator operation is such that the output is a
logical one (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than
the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. The comparator may be
configured to cause an interrupt when the output value changes.
Comparator Configuration
The comparator has a control register, CMP1. The control register is
shown in Figure 2.
The overall connections to the comparator are shown in Figure 3.
There are eight possible configurations for the comparator, as
determined by the control bits in the CMP1 register: CP1, CN1, and
OE1. These configurations are shown in Figure 4. The comparator
functions down to a V
DD
of 3.0V.
When the comparator is first enabled, the comparator output and
interrupt flag are not guaranteed to be stable for 10 microseconds.
The comparator interrupt should not be enabled during that time,
and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt
service.
BIT
CMP1.7, 6
CMP1.5
SYMBOL
—
CE1
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Comparator enable. When set by software, the corresponding comparator function is enabled.
Comparator output is stable 10 microseconds after CE1 is first set.
Comparator positive input select. When 0, CIN1A is selected as the positive comparator input. When
1, CIN1B is selected as the positive comparator input.
Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as
the negative comparator input. When 1, the internal comparator reference V
ref
is selected as the
negative comparator input.
Output enable. When 1, the comparator output is connected to the CMP1 pin if the comparator is
enabled (CE1 = 1). This output is asynchronous to the CPU clock.
Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the
comparator is disabled (CE1 = 0).
Comparator interrupt flag. This bit is set by hardware whenever the comparator output CO1 changes
state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by
software and when the comparator is disabled (CE1 = 0).
CMP1.4
CP1
CMP1.3
CN1
CMP1.2
OE1
CMP1.1
CO1
CMP1.0
CMF1
CMF1
SU01531
CO1
OE1
CN1
CP1
CE1
—
—
0
1
2
3
4
5
6
7
CMP1
Reset Value: 00h
Address: ACh
Not Bit Addressable
Figure 2. Comparator Control Register (CMP1)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| P87LPC760BDH | 功能描述:8位微控制器 -MCU 80C51 1K/128 OTP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC760BDH,112 | 功能描述:8位微控制器 -MCU 80C51 1K/128 OTP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC760BDH,118 | 功能描述:8位微控制器 -MCU 14 PIN MCU 1KBYTE OTP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC760BN | 功能描述:8位微控制器 -MCU 1K/128 OTP 2.7-6V COMM DIP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC760BN,112 | 功能描述:8位微控制器 -MCU 1K/128 OTP 2.7-6V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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