- 您現在的位置：買賣IC網 > PDF目錄376314 > RM7000-266T (PMC-SIERRA INC) RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released PDF資料下載
參數資料
| 型號： | RM7000-266T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 266 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數： | 13/54頁 |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-266T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
13
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Figure 3 Instruction Issue Paradigm
The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies
more completely the instructions within each class.
Table 2 Dual Issue Instruction Classes
integer
add, sub, or, xor, shift,
etc.
The symmetric superscalar capability of the RM7000, in combination with its low latency integer
execution units and high-throughput fully pipelined floating-point execution unit, provides
unparalleled price/performance in computational intensive embedded applications.
Pipeline
4.3
The logical length of both the F and M pipelines is five stages with state committing in the register
write, or W, pipe stage. The physical length of the floating-point execution pipeline is actually
seven stages but this is completely transparent to the user.
Figure 4 shows instruction execution within the RM7000 when instructions are issuing
simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be
executing simultaneously. This figure presents a somewhat simplistic view of the processors
operation however since the out-of-order completion of loads, stores, and long latency floating-
point operations can result in there being even more instructions in process than what is shown.
load/store
lw, sw, ld, sd, ldc1,
sdc1, mov, movc,
fmov, etc.
floating-point
fadd, fsub, fmult,
fmadd, fdiv, fcmp,
fsqrt, etc.
branch
beq, bne, bCzT,
bCzF, j, etc.
F Pipe
Integer
M Pipe
Integer
F Pipe
FP
M Pipe
FP
Cache
Instruction
Unit
Dispatch
F Pipe IBus
M Pipe IBus
相關PDF資料 |
PDF描述 |
|---|---|
| RM7000-300S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7935 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RM7965 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RMLA3565-58 | Wideband Low Noise MMIC Amplifier |
相關代理商/技術參數 |
參數描述 |
|---|---|
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
| RM7000A-350T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
發布緊急采購，3分鐘左右您將得到回復。