- 您現在的位置：買賣IC網 > PDF目錄376314 > RM7000-266T (PMC-SIERRA INC) RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released PDF資料下載
參數資料
| 型號： | RM7000-266T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 266 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數： | 5/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-266T |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
5
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1
Features ..................................................................................................................................9
2
Block Diagram .......................................................................................................................10
3
Description ............................................................................................................................11
4
Hardware Overview ...............................................................................................................12
4.1
CPU Registers .............................................................................................................12
4.2
Superscalar Dispatch ...................................................................................................12
4.3
Pipeline ........................................................................................................................13
4.4
Integer Unit ..................................................................................................................14
4.5
ALU ..............................................................................................................................15
4.6
Integer Multiply/Divide ..................................................................................................15
4.7
Floating-Point Coprocessor ..........................................................................................16
4.8
Floating-Point Unit .......................................................................................................16
4.9
Floating-Point General Register File ............................................................................16
4.10 System Control Coprocessor (CP0) .............................................................................17
4.11 System Control Coprocessor Registers .......................................................................18
4.12 Virtual to Physical Address Mapping ............................................................................19
4.13 Joint TLB ......................................................................................................................20
4.14 Instruction TLB .............................................................................................................20
4.15 Data TLB ......................................................................................................................20
4.16 Cache Memory .............................................................................................................21
4.17 Instruction Cache .........................................................................................................21
4.18 Data Cache ..................................................................................................................21
4.19 Secondary Cache ........................................................................................................23
4.20 Secondary Caching Protocols ......................................................................................24
4.21 Tertiary Cache .............................................................................................................24
4.22 Cache Locking .............................................................................................................26
4.23 Cache Management .....................................................................................................26
4.24 Primary Write Buffer .....................................................................................................27
4.25 System Interface ..........................................................................................................27
4.26 System Address/Data Bus ...........................................................................................28
4.27 System Command Bus ................................................................................................28
4.28 Handshake Signals ......................................................................................................28
4.29 System Interface Operation .........................................................................................29
相關PDF資料 |
PDF描述 |
|---|---|
| RM7000-300S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7935 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RM7965 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RMLA3565-58 | Wideband Low Noise MMIC Amplifier |
相關代理商/技術參數 |
參數描述 |
|---|---|
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
| RM7000A-350T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
發布緊急采購，3分鐘左右您將得到回復。