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參數資料
| 型號： | RM7000-266T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 266 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁數： | 18/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-266T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
18
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
4.11 System Control Coprocessor Registers
The RM7000 incorporates all system control coprocessor (CP0) registers internally. These
registers provide the path through which the virtual memory system
’
s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM7000 includes registers to
implement a real-time cycle counting facility, to aid in cache and system diagnostics, and to assist
in data error detection.
To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7000,
both the data and control register spaces of CP0 are supported by the RM7000. In the data register
space, that is the space accessed using the
MFC0
and
MTC0
instructions, the RM7000 supports
the same registers as found in the RM5200, R4000 and R5000 families. In the control space, that is
the space accessed by the previously unused
CTC0
and
CFC0
instructions, the RM7000 supports
five new registers. The first three of these new 32-bit registers support the enhanced interrupt
handling capabilities and are the Interrupt Control, Interrupt Priority Level Lo (IPLLO), and
Interrupt Priority Level Hi (IPLHI) registers. These registers are described further in the section on
interrupt handling. The other two registers, Imprecise Error 1 and Imprecise Error 2, have been
added to help diagnose bus errors which occur on non-blocking memory references.
Figure 5 shows the CP0 registers.
Figure 5 CP0 Registers
0
47
TLB
(entries protected
from TLBWR)
Wired
6*
Random
1*
Index
0*
Status
12*
Cause
13*
EPC
14*
ErrorEPC
30*
Watch1
18*
PRId
15*
Config
16*
TagHi
29*
TagLo
28*
ECC
26*
CacheErr
27*
LLAddr
17*
Watch2
19*
XContext
20*
Used for memory
management
Used for exception
processing
Watch Mask
24*
* Register number
Info
7*
相關PDF資料 |
PDF描述 |
|---|---|
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| RM7000-300T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
| RM7000A-350T | 制造商:PMC-Sierra 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
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