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參數資料
| 型號： | S29GL016A10FAI020 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| 封裝： | 13 X 11 MM, FBGA-64 |
| 文件頁數： | 43/95頁 |
| 文件大小： | 3585K |
| 代理商： | S29GL016A10FAI020 |
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48
S29GL-A
S29GL-A_00_A12 May 21, 2008
Da ta
Sh e e t
7.11.2
Factory Locked: Secured Silicon Sector Programmed and Protected At the
Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory.
The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte
random ESN at addresses 000000h–000007h. Please contact your sales representative for details on
ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion programming
service (Customer Factory Locked). The devices are then shipped from the factory with the Secured Silicon
Sector permanently locked. Contact your sales representative for details on using the Spansion programming
service.
7.12
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group without
using VID. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or
last sector group independently of whether those sector groups were protected or unprotected. Note that if
WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See
the table in DC Characteristics on page 70.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was
previously set to be protected or unprotected using the method described in Sector Group Protection
and Unprotection on page 41. Note that WP# contains an internal pull-up; when unconnected, WP# is
at VIH.
7.13
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 10.2 on page 61 and Table 10.1 on page 62 for command
definitions). In addition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
7.13.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater
than VLKO.
7.13.2
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
7.13.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
7.13.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
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