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參數資料
| 型號： | SC403MLTRT |
| 廠商： | Semtech |
| 文件頁數： | 13/32頁 |
| 文件大?。?/td> | 741K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標準包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 可調至 0.75V，200mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC403MLDKR |
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SC403
13
Pin Descriptions
Pin # Pin Name Pin Function
1
FB
Feedback input for switching regulator used to program the output voltage connect to an external resis-
tor divider from VOUT to AGND.
2
VOUT
Switcher output voltage sense pin also the input to the internal switch-over between VOUT and VLDO.
The voltage at this pin must be less than or equal to the voltage at the VDD pin.
3
VDD
Bias supply for the IC when using the internal LDO as a bias power supply, the VDD is the LDO output.
When using an external power supply to bias the IC, the LDO output should be disabled.
4, 30, PAD 1 AGND Analog ground
5
FBL
Feedback input for the internal LDO connect to an external resistor divider from VDD to AGND to pro-
gram the LDO output.
6, 9-11,
PAD 2
VIN Input supply voltage
7
SS
The soft start time is programmed by an internal current source charging a capacitor on this pin.
8
BST
Bootstrap pin connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the
high-side gate drive.
12
NC No connection
13
LXBST LX Boost connect to the BST capacitor.
23-25, PAD 3
LX Switching (phase) node
14
NC No connection
15-22
PGND Power ground
26
PGOOD
Open-drain power good indicator high impedance indicates power is good. An external pull-up
resistor is required.
27
ILIM Current limit sense pin used to program the current limit by connecting a resistor from ILIM to LXS.
28
LXS LX sense connects to R
ILIM
.
29
EN/PSV
Enable/power-save input for the switching regulator connect to AGND to disable the switching regulator.
Float to operate in forced continuous mode (PSAVE disabled). Connect to VDD to operate with ultrasonic
PSAVE mode enabled.
31
TON On-time programming input set the on-time by connecting through a resistor to AGND.
32
ENL
Enable input for the LDO connect ENL to AGND to disable the LDO. Drive with logic signal for logic con-
trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND pins.
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