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參數(shù)資料
型號(hào): SC403MLTRT
廠商: Semtech
文件頁(yè)數(shù): 28/32頁(yè)
文件大小: 741K
描述: IC REG DL BCK/LINEAR SYNC 32MLPQ
標(biāo)準(zhǔn)包裝: 1
系列: EcoSpeed®, SmartDrive™
拓?fù)洌?/td> 降壓(降壓)同步(1),線(xiàn)性(LDO)(1)
功能: 任何功能
輸出數(shù): 2
頻率 - 開(kāi)關(guān): 1MHz
電壓/電流 - 輸出 1: 可調(diào)至 0.75V,6A
電壓/電流 - 輸出 2: 可調(diào)至 0.75V,200mA
帶 LED 驅(qū)動(dòng)器: 無(wú)
帶監(jiān)控器: 無(wú)
帶序列發(fā)生器:
電源電壓: 3 V ~ 28 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-MLPQ(5x5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): SC403MLDKR
SC403
28
Applications Information (continued)
All other decoupling capacitors must be located
as close as possible to the IC.
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the
device.
The PGND copper area between the input
capacitors, output capacitors, and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
Connect PGND to AGND with a short trace or
0& resistor. This connection should be as close
to the device as possible.
"
"
"
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VOUT Plane
on Top layer
L
CLDO
C
IN
CFF
RFB2
RFB1
RILIM
RLDO2
RLDO1
LX plane on inner
or bottom layer
All components
shown Top Side
AGND plane on
inner layer
V
IN
 plane on inner
or bottom layer
RGND  AGND connects to
PGND close to the IC
Pin 1 marking
IC with vias for
LX, AGND, VIN
C
OUT
PGND on inner
or bottom layer
PGND
PGND on
Top Layer
V5V Decoupling Capacitor
RGND
Figure 15  PCB Layout
PCB Layout Guidelines
The optimum layout for the SC403 is shown in Figure 15.
This layout shows an integrated FET buck regulator with a
maximum current of 6A. The total PCB area is approxi-
mately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
CIN and COUT placement and current loops
IC Decoupling Capacitors
A 0.1 糉 capacitor must be located as close as
possible to the IC and directly connected to pins
3 (VDD) and 4 (AGND).
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