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參數(shù)資料
| 型號(hào)： | SC403MLTRT |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 24/32頁(yè) |
| 文件大小： | 741K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調(diào)至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 可調(diào)至 0.75V，200mA |
| 帶 LED 驅(qū)動(dòng)器： | 無(wú) |
| 帶監(jiān)控器： | 無(wú) |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | SC403MLDKR |
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SC403
24
Applications Information (continued)
The design goal is that the output voltage regulation be
?% under static conditions. The internal 750mV refer-
ence tolerance is ?%. Allowing ?% tolerance from the
FB resistor divider, this allows 2% tolerance due to V
OUT
ripple. Since this 2% error comes from 1/2 of the ripple
voltage, the allowable ripple is 4%, or 60mV for a 1.5V
output.
The maximum ripple current of 3.7A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
A
7
.
3
mV
60
I
V
ESR
RIPPLEMAX
RIPPLE
MAX
ESR
MAX
= 16.2 m&
The output capacitance is usually chosen to meet tran-
sient requirements. A worst-case load release, from
maximum load to no load at the exact moment when the
inductor current is at the peak, determines the required
capacitance. If the load release is instantaneous (load
changes from maximum to zero in < 1祍), the output
capacitor must absorb all the inductors stored energy.
This will cause a peak voltage on the capacitor requiring a
capacitance provided by the following equation.
2
OUT
2
PEAK
2
RIPPLEMAX
OUT
MIN
V
V
I
2
1
I
L
COUT
Assuming a peak voltage V
PEAK
of 1.6V (100mV rise upon
load release), and a 6A load release, the required capaci-
tance is shown by the next equation.
2
2
2
MIN
V
5
.
1
V
6
.
1
A
7
.
3
2
1
A
6
H
5
.
1
COUT
COUT
MIN
= 298礔
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-V
OUT
. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capaci-
tance for a given dI
LOAD
/dt.
Peak inductor current is shown by the next equation.
I
LPK
= I
MAX
+ 1/2 x I
RIPPLEMAX
I
LPK
= 6 + 1/2 x 3.7 = 7.9A
dt
dl
Current
Load
of
change
of
Rate
LOAD
I
MAX
= maximum load release = 6A
OUT
PK
LOAD
MAX
OUT
LPK
LPK
OUT
V
V
2
dt
dl
I
V
I
L
I
C
Example
s
1
A
2
dt
dl
LOAD
This would cause the output current to move from 6A to
0A in 3.0祍, giving the minimum output capacitance
requirement shown in the following equation.
V
5
.
1
V
6
.
1
2
s
1
2
6
5
.
1
9
.
7
H
5
.
1
A
9
.
7
C
OUT
C
OUT
= 194 礔
Note that C
OUT
is much smaller in this example, 194礔
compared to 298礔 based on a worst-case load release. To
meet the maximum design criteria of minimum 298礔
and maximum 16m& ESR, select one capacitor rated at
330礔 and 9m& ESR.
It is recommended that an additional small capacitor be
placed in parallel with C
OUT
in order to filter high frequency
switching noise.
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