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參數資料
| 型號： | SC403MLTRT |
| 廠商： | Semtech |
| 文件頁數： | 26/32頁 |
| 文件大小： | 741K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標準包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數： | 2 |
| 頻率 - 開關： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 可調至 0.75V，200mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC403MLDKR |
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SC403
26
Applications Information (continued)
sw
OUT
MIN
f
C
2
3
SR
E
Using Ceramic Output Capacitors
For applications using ceramic output capacitors, the ESR
is normally too small to meet the above ESR criteria. In
these applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in Figure 14. This network creates a ramp voltage
across C
L
, analogous to the ramp voltage generated across
the ESR of a standard capacitor. This ramp is then capaci-
tively coupled into the FB pin via capacitor C
C
.
R1
R2
FB
pin
C
C
C
OUT
L
Low-
side
High-
side
C
L
R
L
Virtual
ESR
Network
Figure 14 Virtual ESR Ramp Circuit
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is limited by the fixed 80ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calcu-
lated using worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
)
MAX
(
OFF
)
MIN
(
ON
)
MIN
(
ON
t
t
t
DUTY
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (V
OUT
Controller)
Three factors affect V
OUT
accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static condi-
tions it trips when the feedback pin is 750mV, +1%.
The on-time pulse from the SC403 in the design example
is calculated to give a pseudo-fixed frequency of 300kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
constant on-time converters regulate to the valley of the
output ripple, ?of the output ripple appears as a DC regu-
lation error. For example, if the output ripple is 50mV with
V
IN
= 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
80mV with V
IN
= 25V, then the measured DC output will be
40mV above the comparator trip. The best way to mini-
mize this effect is to minimize the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Switching Frequency Variation
The switching frequency will vary depending upon line
and load conditions. The line variation is a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
V
IN
increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
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