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參數資料
| 型號： | TFP401AMPZPEP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 19/21頁 |
| 文件大小： | 460K |
| 代理商： | TFP401AMPZPEP |
AC ELECTRICAL CHARACTERISTICS
www.ti.com .................................................................................................................................................................................................. SLDS160 – MARCH 2009
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VID(2)
Differential input sensitivity(1)
150
1560
mVp-p
tps
Analog input intra-pair (+ to -)
0.4
tbit
(3)
differential skew (2)
tccs
Analog Input inter-pair or
1
tpix
(4)
channel-to-channel skew (2)
tijit
Worse case differential input clock
50
ps
jitter tolerance(5), (2)(6)
tf1
Fall time of data and control
ST = Low,
CL=5 pF
2.4
ns
signals(7), (8)(6)
ST = High,
CL=10 pF
1.9
tr1
Rise time of data and control
ST = Low,
CL=5 pF
2.4
ns
signals(7), (8)(6)
ST = High,
CL=10 pF
1.9
tr2
Rise time of ODCK clock(7)(6)
ST = Low,
CL=5 pF
2.4
ns
ST = High,
CL=10 pF
1.9
tf2
Fall time of ODCK clock(7)(6)
ST = Low,
CL=5 pF
2.4
ns
ST = High,
CL=10 pF
1.9
tsu1
Setup time, data and control signal to
1 pixel/clock, PIXS = low,
1.8
falling edge of ODCK(6)
OCK_INV = low
2 pixel/clock, PIXS = high,
3.8
ns
STAG = high, OCK_INV = low
2 pixel and STAG, PIXS = high,
0.6
STAG = low, OCK_INV = low
th1
Hold time, data and control signal to
1 pixel/clock, PIXS = low,
0.6
falling edge of ODCK(6)
OCK_INV = low
2 pixel and STAG, PIXS = high,
2.5
ns
STAG = low, OCK_INV = low
2 pixel/clock, PIXS = high,
2.9
STAG = high, OCK_INV = low
tsu2
Setup time, data and control signal to
1 pixel/clock, PIXS = low,
2.1
rising edge of ODCK(6)
OCK_INV = high
2 pixel/clock, PIXS = high,
4
ns
STAG = high, OCK_INV = high
2 pixel and STAG, PIXS = high,
1.5
STAG = low, OCK_INV = high
th2
Hold time, data and control signal to
1 pixel/clock, PIXS = low,
0.3
rising edge of ODCK(6)
OCK_INV = high
2 pixel and STAG, PIXS = high,
2.4
ns
STAG = low, OCK_INV = high
2 pixel/clock, PIXS = high,
2.1
STAG = high, OCK_INV = high
fODCK
ODCK frequency
PIX = Low (1-PIX/CLK)
25
165
MHz
PIX = High (2-PIX/CLK)
12.5
82.5
ODCK duty-cycle
45%
60%
75%
tpd(PDL)
Propagation delay time from PD low
9
ns
to Hi-Z outputs(6)
(1)
Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
(2)
By characterization
(3)
tbit is 1/10 the pixel time, tpix
(4)
tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when
in 2-pixel/clock mode.
(5)
Measured differentially at 50% crossing using ODCK output clock as trigger.
(6)
Not Production Test
(7)
Rise and fall times measured as time between 20% and 80% of signal amplitude.
(8)
Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]
Copyright 2009, Texas Instruments Incorporated
7
Product Folder Link(s): TFP401A-EP
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