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參數資料
| 型號： | TFP401AMPZPEP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 5/21頁 |
| 文件大小： | 460K |
| 代理商： | TFP401AMPZPEP |
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+
Internal Termination
at 50
AVDD
DVI Compliant Cable
DATA
TI TFP401/401A
Receiver
DVI
Transmitter
Current
Source
1/2 VIDIFF
AVCC
AVCC - 1/2 VIDIFF
a ) Single-Ended Input Signal
+ 1/2 VIDIFF
- 1/2 VIDIFF
VIDIFF
b) Differential Input Signal
TFP401A INCORPORATES HSYNC JITTER IMMUNITY
www.ti.com .................................................................................................................................................................................................. SLDS160 – MARCH 2009
Figure 14. TMDS Differential Input and Transmitter Connection
Figure 15. TMDS Inputs
Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals
during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal
in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and
if the position of HSYNC shifts continuously, the receiver can lose track of the input timing and pixel noise will
occur on the display. For this reason, a DVI compliant receiver with HSYNC jitter immunity should be used in all
displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.
The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant
transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the
location of HSYNC. The TFP401A receiver uses the DE and clock signals recreate stable vertical and horizontal
sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted to the nearest eighth bit
boundary, producing a stable output with respect to data, as shown in Figure 16. This will ensure accurate data
synchronization at the input of the display timing controller.
Copyright 2009, Texas Instruments Incorporated
13
Product Folder Link(s): TFP401A-EP
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TFP401APZP | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr 165MHz HSYNC fix RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401APZPG4 | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401PZP | 功能描述:顯示接口集成電路 PanelBus DVI Receiver 165MHz RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401PZPG4 | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP403 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TI PANEBUS DIGITAL RECEIVER |
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