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參數(shù)資料
| 型號： | TFP401AMPZPEP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 460K |
| 代理商： | TFP401AMPZPEP |
TFP401A CLOCKING AND DATA SYNCHRONIZATION
TFP401A TMDS INPUT LEVELS AND INPUT IMPEDANCE MATCHING
SLDS160 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
The TFP401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time, Tpix.
The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on Rx[2:0]
contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the
required pixel rate to support an UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is
10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate
channels (or twisted-pair wires) of long distances (3-5 meters), phase synchronization between the data steams
and the input reference clock is not specified. In addition, skew between the three data channels is common. The
TFP401A uses a 4x oversampling scheme of the input data streams to achieve reliable synchronization with up
to 1-Tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections
and external noise sources is also typical of high speed serial data transmission, hence the TFP401A's design
for high jitter tolerance.
The input clock to the TFP401A is conditioned by a phase-locked-loop (PLL) to remove high-frequency jitter from
the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data streams
(4x oversampling). During active display the pixel data is encoded to be transition minimized, whereas in blank,
the control data is encoded to be transition maximized. A DVI compliant transmitter is required to transmit in
blank for a minimum period of time, 128-Tpix, to specify sufficient time for data synchronization when the receiver
sees a transition maximized code. Synchronization during blank, when the data is transition maximized, specifies
reliable data bit boundary detection. Phase synchronization to the data streams is unique for each of the three
input channels and is maintained as long as the link remains active.
The TMDS inputs to the TFP401A receiver have a fixed single-ended termination to AVDD The TFP401A is
internally optimized using a laser trim process to precisely fix the impedance at 50 W. The device functions
normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets.
The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching
to standard 50-W DVI cables.
Figure 14 shows a conceptual schematic of a DVI transmitter and TFP401A receiver connection. A transmitter
drives the twisted pair cable via a current source, usually achieved with an open-drain type output driver. The
internal resistor, which is matched to the cable impedance, at the TFP401A input provides a pullup to AVDD .
Naturally, when the transmitter is disconnected and the TFP401A DVI inputs are left unconnected, the TFP401A
receiver inputs pullup to AVDD. The single ended differential signal and full differential signal is shown in
Figure 15. The TFP401A is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with
common mode voltages ranging from (AVDD-300 mV) to (AVDD-37 mV).
12
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TFP401A-EP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TFP401APZP | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr 165MHz HSYNC fix RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401APZPG4 | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401PZP | 功能描述:顯示接口集成電路 PanelBus DVI Receiver 165MHz RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401PZPG4 | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP403 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TI PANEBUS DIGITAL RECEIVER |
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