
FUNDAMENTAL OPERATION
TMDS PIXEL DATA AND CONTROL SIGNAL ENCODING
www.ti.com .................................................................................................................................................................................................. SLDS160 – MARCH 2009
The TFP401A is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel
display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a
host, usually a PC or workstation, contains a TMDS compatible transmitter that receives 24 bit pixel data along
with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit
for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will
require a TMDS compatible receiver like the TI TFP401A to decode the serial bit stream back to the same 24 bit
pixel data and control signals that originated at the host. This decoded data can then be applied directly to the
flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by
distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display
resolutions up to SXGA a high bandwidth receiver with good jitter and skew tolerance is required.
TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a
given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and
zeros previously sent and transmits the character that will minimize the number of transitions and approximate a
dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active
display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user
defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time.
Blanking-time is when DE = low. The following table maps the received input data to appropriate TMDS input
channel in a DVI compliant system.
RECEIVED PIXEL DATA
OUTPUT PINS
INPUT CHANNEL
ACTIVE DISPLAY DE = HIGH
(VALID FOR DE = HIGH)
Red[7:0]
Channel - 2 (Rx2 +)
QE[23:16] QO[23:16]
Green[7:0]
Channel - 1 (Rx1 +)
QE[15:8] QO[15:8]
Blue[7:0]
Channel - 0 (Rx0 +)
QE[7:0] QO[7:0]
RECEIVED CONTROL DATA
UTPUT PINS
INPUT CHANNEL
BLANKING DE = LOW
(VALID FOR DE = LOW)
CTL[3:2]
Channel - 2 (Rx2 +)
CTL[3:2]
CTL[1: 0] (1)
Channel - 1 (Rx1 +)
CTL1
HSYNC, VSYNC
Channel - 0 (Rx0 +)
HSYNC, VSYNC
(1)
Some TMDS transmitters transmit a CTL0 signal. The TFP401A decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is
not available as a TFP401A output.
The TFP401A discriminates between valid pixel TMDS characters and control TMDS characters to determine the
state of active display versus blanking, i.e., state of DE.
Copyright 2009, Texas Instruments Incorporated
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