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參數資料
| 型號： | THS0842IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 18/30頁 |
| 文件大小： | 503K |
| 代理商： | THS0842IPFBG4 |
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THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
digital inputs
The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal
pulldown resistor to connect to digital ground. This provides a default active operation mode using internal
references when left unconnected.
The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be
minimized by proper termination of the signal close to the THS0842. An important cause of performance
degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the
ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by
its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2N) of a signal
that needs to be sampled and the maximum amount of aperture error dtmax that is tolerable. The following
formula shows the relation:
dtmax + 1 B p f2
N
)1
As an example, for an 8-bit converter with a 15-MHz input, the jitter needs to be kept <41 pS in order not to have
changes in the LSB of the ADC output due to the total aperture error.
digital outputs
The output of THS0842 is straight binary code. Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading
causes higher dynamic output currents and can increase noise coupling into the device analog front end. To
drive higher loads, use an output buffer is recommended. See Figure 25 through Figure 28 for examples.
When clocking output data from the THS0842, it is important to observe its timing relation to COUT. See Note
6 in the specification section for more details.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS0842PFB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT |
| THS10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| THS10064 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS10064CDA | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064CDAG4 | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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