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參數資料
| 型號： | THS0842IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 25/30頁 |
| 文件大小： | 503K |
| 代理商： | THS0842IPFBG4 |
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THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AVDD
27, 37, 41
I
Analog supply voltage
AVSS
28, 36, 40,
46
I
Analog ground
BG
29
O
Band gap reference voltage. A 1-
F capacitor with a 0.1-F capacitor in parallel should be connected
between this terminal and AVSS for external filtering.
CLK
47
I
Clock input. The input is sampled on each rising edge of CLK.
CML
32
O
Common mode level. This voltage is equal to (AVDD – AVSS)/2. An external 1-F capacitor with a 0.1-F
capacitor in parallel should be connected between this terminal and AVSS.
COUT
26
O
Latch clock for the data outputs
COUT
25
O
Inverted latch clock for the data outputs
DB7 – DB0
4 – 11
O
Data outputs. D7 is the MSB. This is the second bus. Data is output from the Q channel when dual bus
output mode is selected. Pin SELB selects the output mode.
DRVDD
1, 13
I
Supply voltage for output drivers
DRVSS
12, 24
I
Ground for digital output drivers
DA7 – DA0
16 – 23
I
Data outputs for bus A. D7 is MSB. This is the primary bus. Data from both input channels can be output
on this bus or data from the I channel only. Pin SELB selects the output mode.
DVDD
45
I
Digital supply voltage
DVSS
43
I
Digital ground
I–
39
I
Negative input for analog channel 0.
I+
38
I
Positive input for analog channel 0.
NC
2,3,14,15
No connect. Reserved for future use
OE
48
I
Output enable. A high on this terminal will disable the output bus.
PWDN_REF
33
I
Power down for internal reference voltages. A high on this terminal will disable the internal reference
circuit.
Q–
35
I
Negative input for analog channel 1
Q+
34
I
Positive input for analog channel 1
REFB
30
I/O
Reference voltage bottom. The voltage at this terminal defines the bottom reference voltage for the ADC.
Sufficient filtering should be applied to this input. A 1-
F capacitor with a 0.1-F capacitor in parallel should
be connected between REFB and AVSS. Additionally, a 0.1-F capacitor can be connected between REFT
and REFB.
REFT
31
I/O
Reference voltage top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient
filtering should be applied to this input. A 1-
F capacitor with a 0.1-F capacitor in parallel should be
connected between REFT and AVSS. Additionally, a 0.1-F capacitor can be connected between REFT
and REFB.
SELB
44
I
Selects either single bus or data output or dual bus output data output. A low selects dual bus data output.
STBY
42
I
Standby input. A high level on this terminal will power down the device.
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| THS10064CDA | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064CDAG4 | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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