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參數資料
| 型號： | THS0842IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 28/30頁 |
| 文件大?。?/td> | 503K |
| 代理商： | THS0842IPFBG4 |
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THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use
of internal voltage references, AVDD = DVDD = DRVDD = 3 V, TA = TMIN to TMAX, dual output bus mode
(unless otherwise noted) (continued)
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Integral nonlinearity (INL), best-fit
See Note 1
TA = –40°C to 85°C
–2.2
±1.5
2.2
LSB
Differential nonlinearity (DNL)
See Note 2
TA = –40°C to 85°C
–1
±0.7
2
LSB
Offset error
TA =40°Cto85°C (see Note 3)
±0.1
5
%FS
Gain error
TA = –40°C to 85°C, (see Note 3)
±7.1
%FS
Offset match
TA = –40°C to 85°C, (see Note 4)
–1
±0.1
1
LSB
Gain match
TA = –40°C to 85°C, (see Note 5)
–5
1
LSB
Missing codes – no missing codes assured
NOTES:
1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition.
The deviation is measured from the center of each particular code to the best fit line between these two endpoints.
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level – first transition level)
÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.
3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).
Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).
4. Offset match is the change in offset error between I and Q channels.
5. Gain match is the change in gain error between I and Q channels.
analog input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CI
Input capacitance
4
pF
reference input (AVDD = DVDD = DRVDD = 3.6 V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Rref
Reference input resistance
200
Iref
Reference input current
5
mA
reference outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(REFT)
Reference top voltage
AVDD =3V
2 + [(AVDD – 3)/2]
V
V(REFB)
Reference bottom voltage
AVDD = 3 V
1 + [(AVDD – 3)/2]
V
VREFB–VREFB
Absolute min/max values valid
and tested for AVDD = 3 V
0.9
1
1.3
V
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