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參數資料
| 型號： | THS0842IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 29/30頁 |
| 文件大小： | 503K |
| 代理商： | THS0842IPFBG4 |
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THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions with fCLK = 80 MSPS and use
of internal voltage references, AVDD = DVDD = DRVDD = 3 V, TA = TMIN to TMAX, dual output bus mode
(unless otherwise noted) (continued)
dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fin = 1 MHz
6.6
6.9
Effective number of bits, ENOB
fin = 15 MHz
6.4
6.8
Bits
fin = 20 MHz
6.4
6.8
fin = 1 MHz
41.5
43.5
Signal-to-total harmonic distortion + noise, S/(THD+N)
fin = 15 MHz
40
42.5
dB
fin = 20 MHz
40
42.5
fin = 1 MHz
–51
–46
Total harmonic distortion (THD)
fin = 15 MHz
–48.5
–44
dB
fin = 20 MHz
–48.5
–44
fin = 1 MHz
48
53
Spurious free dynamic range (SFDR)
fin = 15 MHz
47
52.2
dB
fin = 20 MHz
46
52
Analog input full-power bandwidth, BW
See Note 6
600
MHz
Intermodulation distortion
f1 = 1 MHz, f2 = 1.02 MHz
50
dBc
I/Q channel crosstalk
AVDD = DVDD = DRVDD = 3.3 V
–52
dBc
Based on analog input voltage of – 1 dBFS referenced to a 1.3 Vpp full-scale input range.
NOTE 6: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which
an extra 3 dB attenuation is observed in the reconstructed output signal.
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f lk
Maximum clock rate (see Note 7)
80
MHz
fclk
Minimum clock rate
10
kHz
td(O)
Output delay time (see timing diagram)
CL = 10 pF
9
ns
th(O)
Output hold time from COUT or COUT to data invalid
2
ns
td( i )
Pipeline delay (latency)
I data
5.5
CLK
td(pipe)
Pipeline delay (latency)
Q data
6.5
cycles
td(a)
Aperture delay time
3
ns
tj(a)
Aperture jitter
1.5
ps, rms
tdis
Disable time, OE rising to Hi-Z
5
ns
ten
Enable time, OE falling to valid data
5
ns
tsu(O)
Output setup time from data to COUT or COUT
8
7
ns
NOTE 7: Conversion rate is 1/2 the clock rate, fclk.
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| THS10064CDA | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10064CDAG4 | 功能描述:模數轉換器 - ADC 10-Bit 6 MSPS Quad Ch DSP/uP Ifc RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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