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參數資料
| 型號： | THS8083APZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 21/63頁 |
| 文件大小： | 320K |
| 代理商： | THS8083APZP |
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3.11.16 Register Name: PLL_CTRL
Subaddress: 0F (R/W)
X
MSB
LSB
X
DISABLE_PFD
SEL_ADCCLK
INV2
DIV2
INV3
DIV3
DISABLE_PFD:
Disables updating of the DTO increment (i.e., keeps DTO output frequency constant and independent of the
incoming HS frequency). This effect is similar as opening the PLL loop.
0 = PFD enabled
1 = PFD disabled (default): the DTO runs at a constant frequency, as determined by NOM_INC. This means
the output frequency returns to the nominal value and further updating of the DTO output frequency is
avoided (the PLL loop is open). This is chosen as the default mode to avoid false random frequency changes
by the DTO caused by noise on the HS input. In normal operation the microprocessor periodically checks
the SYNC_DETECT register. If sync is present/absent, then the PFD is enabled/disabled so, frequency drift
is avoided when no input signal is present. Still the panel can be driven then by data with a nominal pixel
frequency.
SEL_ADCCLK:
Selects the PLL clock or the clock signal on the EXT_ADCCLK pin, as the clock source for the ADC channels
0: internal clock selected (default)
1: external clock selected
INV2 :
Selects inverting or noninverting clock output on ADCCLK2 output pin
0: the output is not inverted (default) with respect to the internal ADCCLK1 clock
1: the output is inverted with respect to the internal ADCCLK1 clock
DIV2:
Enables divide-by-2 function on the clock output of ADCCLK2
0: divide by 2 mechanism is disabled (default)
1: divide by 2 mechanism is enabled
INV3:
Selects inverting or noninverting output on DTOCLK3, with respect to the internal DTOCLK3 clock
0: the output is not inverted (default)
1: the output is inverted
DIV3:
Enables divide-by-2 function on the clock output of DTOCLK3
0: divided by 2 mechanism is disabled (default)
1: divided by 2 mechanism is enabled
3.11.17 Register Name: HS_COUNT_0
Subaddress: 10 (R)
HS_COUNT7
MSB
LSB
HS_COUNT6
HS_COUNT5
HS_COUNT4
HS_COUNT3
HS_COUNT2
HS_COUNT1
HS_COUNT0
HS_COUNT[7..0]
HS_COUNT[11..0] holds the last horizontal sync period number (i.e., the number of pixel clock cycles
between the last two HS occurrences). The device updates the value at each active edge of HS. Internal
arbitration logic avoids potential read errors between the register contents and the asynchronous I2C bus.
This value can be read by the microcontroller to derive the line frequency of the incoming video/graphics
format.
Default: (changed during operation)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS8083APZP | 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083 |
| THS8083APZPG4 | 功能描述:視頻模擬/數字化轉換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| THS8083CPZP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS8083EVM | 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk |
| THS8083T | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
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