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參數資料
| 型號： | THS8083APZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數： | 6/63頁 |
| 文件大?。?/td> | 320K |
| 代理商： | THS8083APZP |
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31
3 Functional Description
3.1
Analog Channel
The THS8083A contains three identical analog channels that are independently programmable. Each channel
consists of a clamping circuit, a programmable gain amplifier, and an A/D converter.
3.2
Clamping Circuit
The purpose of clamping is to provide the input signal with a known dc-value. Typically, video signals are ac-coupled
into the part. The signal needs to be level-shifted to fall in the reference voltage range (VREFB...VREFT) of the A/D
converter. By supplying a programmable clamp, the user can shift the input signal with respect to the A/D range. This
has the same effect as keeping the input signal constant and applying offset to both A/D reference voltages while
keeping the VREFTVREFB difference equal. However, no external adjustments are needed with this
implementation.
For video, the clamping circuit can only be active during the non-active video portion of each line to avoid changes
in brightness along the line. Clamping is done during the horizontal blanking interval, either on the back porch of sync
or during the sync tip (in the case of a sync present on at least one of the video channels). If HS is carried on a separate
line, as is typically the case for PC graphics, clamping is done during blanking. When the Y or G input channel contains
an embedded sync, then alternatively clamping can be done during the sync-tip or during the front or back porch of
sync. Only clamping during front- or back-porch of sync is supported on the THS8083A, since it is expected that the
input signal level during clamping, of which position and width are determined by the clamp timing pulse (as shown
later) corresponds to the blanking level. Since the blanking level for RGB type inputs corresponds to a low output code
of the A/D, it makes sense to center the clamp range around an A/D output code of 0. The user can adjust this level
up or down, symmetrically around 0. If the clamping is set such that the blanking level corresponds to a level below
0, the A/D output is clipped at code 0.
CLP
VIN
Reference Level
PGA 1
PGA 2
ADC
8
6
Reference Level
Bottom/Mid
8
Offset
DAC
Clamp DAC
PGA Gain Control
Clamp Control
CC
Figure 31. Analog Channel Architecture
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS8083APZP | 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083 |
| THS8083APZPG4 | 功能描述:視頻模擬/數字化轉換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| THS8083CPZP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS8083EVM | 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk |
| THS8083T | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
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