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參數(shù)資料
型號(hào)： THS8083APZP
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 8/63頁(yè)
文件大?。?/td> 320K
代理商： THS8083APZP
33
Alternatively, if an external sync separator is present that generates HS and VS from CS, the separated signals can
be fed to the corresponding inputs on the THS8083A and PFD_FREEZE can be left unused. As long as HS has one
pulse per line, the PLL can lock correctly and the HS frequency monitoring register will return the correct value. VS
is only used by the field/frame frequency monitoring register and this will return the correct value as long as VS has
one pulse per field/frame. Both options are shown in Figure 24.
Ext. Logic
PFD_FREEZE
CS
THS8083A
HS
Frame Period
PFD_FREEZE High in VBI on Lines Where CS
Has Multiple Rising/Falling Edges Per Line
Option 1: Using PFD_FREEZE
Sync.
Separator
CS
THS8083A
HS
Option 2: Using HS Derived From CS
PFD_FREEZE
VS
Figure 34. Using THS8083A With a Composite Sync
as Note that the slicer only works when no video levels are lower than the blanking level and when the internal clamp
circuit is used. This is normally satisfied for G and Y channels, but not for U and V channels. To prevent unnecessary
toggling of the CS output signal, the CS output is switched off (i.e. HI-Z) automatically when mid-level clamping is
chosen for channel 1 (i.e., CLP1_RG=1 in register <CLP_CTRL>).
The source for the slicer is either Ch1 or the dedicated input CS_IN, as selected by register CS_SEL. It is
recommended to use the dedicated input by ac-coupling the Y/G signal input to both Ch1 and CS_IN (using
independent coupling capacitors). The THS8083A performs independent clamping on both inputs.
NOTE:In this revision-A silicon, PDF_FREEZE keeps the DTO output frequency constant and
disables the phase-frequency detector (PFD) from internally updating its error value at every
active edge of HS (this was not the case in prerevision-A versions). Therefore, when
PFD_FREEZE is asserted, the PLL effectively ignores incoming pulses on the HS terminal.
In this revision-A silicon, users do not need to provide an external dc biasing to the Y/G channel
since now a dedicated input terminal for composite sync slicing is provided. This was not the
case in prerevision-A versions, where the sync could only be extracted from Channel1 and a
clamp diode had to be used to establish an initial clamping level. This method is described in
the following section.
When using the dedicated CS_IN terminal, the G/Y signal should be ac-coupled to this terminal
independently from Ch1, i.e., the G/Y signal is routed via a coupling capacitor to CS_IN and
via a second coupling capacitor to Ch1. This is because the THS8083A imposes an
independent (programmable) clamp level for the sync input.
相關(guān)PDF資料
PDF描述
THS8083APZPG4 SPECIALTY CONSUMER CIRCUIT, PQFP100
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS8083APZP 制造商:Texas Instruments 功能描述:8BIT ADC 80MSPS TRIPLE SMD 8083
THS8083APZPG4 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8B 95MSPS 3.3V Vid & Graphics Dig RoHS:否 制造商:Texas Instruments 輸入信號(hào)類(lèi)型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類(lèi)型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel
THS8083CPZP 制造商:Rochester Electronics LLC 功能描述:- Bulk
THS8083EVM 制造商:Texas Instruments 功能描述:THS8083EVM - Bulk
THS8083T 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL
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