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參數(shù)資料
| 型號(hào)： | TLV320DAC32IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 18/69頁 |
| 文件大小： | 1242K |
| 代理商： | TLV320DAC32IRHBR |
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TDM DATA TRANSFER
N-1
N-2
1
0
N-1
N-2
1
0
word
clock
bit clock
data
in
RightChannelData
LeftChannelData
N-1
N-2
1
0
N-1
N-2
1
0
word
clock
bit clock
data
in
DSP Mode
LeftJustifiedMode
offset
AUDIO DATA CONVERTERS
AUDIO CLOCK GENERATION
www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit
clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed. For
incoming data, the dac simply ignores data on the bus except where it is expected based on the programmed
offset.
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left and right channel data will always be a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left and
right channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
Figure 30 below for the two cases.
Figure 30. DSP Mode and Left Justified Modes, Showing the
Effect of a Programmed Data Word Offset
The TLV320DAC32 supports the following standard audio sampling rates: 8-kHz, 11.025-kHz, 12-kHz, 16-kHz,
22.05-kHz, 24-kHz, 32-kHz, 44.1-kHz, 48-kHz, 88.2-kHz, and 96-kHz.
The data converter is based on the concept of an Fsref rate that is used internal to the part, and it is related to
the actual sampling rates of the dac through a series of ratios. For typical sampling rates, Fsref will be either
44.1-kHz or 48-kHz, although it can realistically be set over a wider range of rates up to 96-kHz, with additional
restrictions applying if the PLL is used. This concept is used to set the sampling rates of the DAC, and also to
enable high quality playback of low sampling rate data, without high frequency audible noise being generated.
The sampling rate of the DAC can be set to Fsref/NDAC or 2*Fsref/NDAC, with NDAC being 1, 1.5, 2, 2.5, 3,
3.5, 4, 4.5, 5, 5.5, or 6.
The audio dac in the TLV320DAC32 needs an internal audio master clock at a frequency of 256*Fsref, which can
be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320DAC32 is shown in Figure 31.
Copyright 2006–2008, Texas Instruments Incorporated
25
Product Folder Link(s): TLV320DAC32
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| TLV320DAC32IRHBRG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Lo-Pwr Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC32IRHBT | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Low Power Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC32IRHBTG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Low Power Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| TLV320DAC33NIZQC | 制造商:Texas Instruments 功能描述: |
| TLV320DAC33NIZQCR | 制造商:Texas Instruments 功能描述: |
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