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參數資料
| 型號： | TMC2491AR2C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 15/36頁 |
| 文件大小： | 208K |
| 代理商： | TMC2491AR2C |
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TMC2490A/TMC2491A
PRODUCT SPECIFICATION
22
Closed Caption Insertion
The TMC2490(1)A includes a exible closed caption pro-
cessor. It may be programmed to insert a closed caption sig-
nal on any line within a range of 16 lines on ODD and/or
EVEN elds.
Closed Caption insertion overrides all other congurations
of the encoder. If it is specied on an active video line, it
takes precedence over the video data and removes NTSC
setup if setup has been programmed for the active video
lines.
Closed Caption Control
Closed caption is turned on by setting CCON HIGH. When-
ever the encoder begins producing a line specied by
CCFLD and CCLINE, it will insert a closed caption line in
its place. If CCRTS is HIGH, the data contained in CCDx
will be sent. IF CCRTS is LOW, Null Bytes (hex 00 with
ODD parity) will be sent.
Line Selection
The line to contain CC data is selected by a combination of
the CCFLD bit and the CCLINE bits. CCLINE is added to
the offset shown in Table 13 to specify the line.
Table 13. Closed Caption Line Selection
Parity Generation
Standard Closed-Caption signals employ ODD parity, which
may be automatically generated by setting CCPAR HIGH.
Alternatively, parity may be generated externally as part of
the bytes to be transmitted, and, with CCPAR LOW, the
entire 16 bits loaded into the CCDx registers will be sent
unchanged.
Operating Sequence
A typical operational sequence for closed-caption insertion
on Line 21 is:
1.
Read Register 22 and check that bit 6 is LOW, indicat-
ing that the CCDx registers are ready to accept data.
2.
If ready, write two bytes of CC data into registers 20 and
21.
Standard
Offset
Field
Lines
525
12
ODD
12-27
274
EVEN
274-289
625
9
ODD
9-24
321
EVEN
321-336
3.
Write into register 22 the proper combination of CCFLD
and CCLINE. CCPAR may be written as desired. Set
CCRTS HIGH.
4.
The CC data is transmitted during the specied line.
As soon as CCDx is transferred into the CC processor (and
CCRTS goes LOW), new data may be loaded into registers
20 and 21. This allows the user to transmit CC data on sev-
eral consecutive lines by loading data for line n+1 while data
is being sent on line n.
Registers 20-21 auto-increment when read or written. Regis-
ter 22 does not. The microcontroller can repeatedly read
register 22 until CCRTS is found to be LOW, then address
register 20 and write three auto-incremented bytes to set up
for the next CC line.
Parallel Microprocessor Interface
The parallel microprocessor interface, active when SER is
HIGH, employs an 11-line interface, with an 8-bit data bus
and one address bit: two addresses are required for device
programming and pointer-register management. Address bit
0 selects between reading/writing the register addresses and
reading/writing register data. When writing, the address is
presented along with a LOW on the R/W pin during the fall-
ing edge of CS. Eight bits of data are presented on D7-0 dur-
ing the subsequent rising edge of CS.
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state tDOZ ns after CS falls. Valid data is
present on D7-0 tDOM after the falling edge of CS.
Table 14. Parallel Port Control
ADR
R/W
Action
1
0
Load D7-0 into Control Register
pointer.
1
Read Control Register pointer on
D7-0.
0
Write D7-0 to addressed Control
Register.
0
1
Read addressed Control Register
on D7-0.
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