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參數資料
| 型號： | TMC2491AR2C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 3/36頁 |
| 文件大?。?/td> | 208K |
| 代理商： | TMC2491AR2C |
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PRODUCT SPECIFICATION
TMC2490A/TMC2491A
11
General Purpose Port
The TMC2490(1)A provides a general purpose I/O port for
system utility functions. Input, output, and sync functions
are implemented. Register 0E is the General Purpose Regis-
ter.
Full functionality is provided when the encoder is in Serial
control mode (SER = LOW). Most of the functions are avail-
able in parallel interface mode (SER = HIGH).
General Purpose Input (serial mode only)
Bits 7 and 6 of Register 0E are general purpose inputs. When
the encoder is in serial control mode, data bits D7 and D6 are
mirrored to these register locations. When Register 0E is
read, the states of bits 7 and 6 reect the TTL logic levels
present on D7 and D6, respectively, at the time of read com-
mand execution. Writing to these bits has no effect.
This function is not available when the encoder is in parallel
control mode.
General Purpose Output
Register 0E read/write bits 5-2 are connected to pins D5-2,
respectively, when the encoder is in serial control mode. The
output pins continually reects the values most recently writ-
ten into register 0E (1 = HIGH, 0 = LOW). Note that these
pins are always driven outputs when the encoder is in serial
control mode.
When register 0E is read, these pins report the values previ-
ously stored in the corresponding register bits, i.e., it acts as
a read/write register. When the encoder is in parallel control
mode, this reading produces the output bit values on the cor-
responding data pins, just as in the serial control mode. How-
ever, the values are only present when reading register 0E.
The controller can command a continuous read on this regis-
ter to produce continuous outputs from these pins.
Burst Flag and Composite Sync (output/
read-only)
Register 0E bit 1 is associated with the encoder burst ag. It
is a 1 (HIGH) from just before the start of the color burst to
just after the end of the burst. It is a 0 (LOW) at all other
times.
Register 0E bit 0 outputs the encoder composite sync status.
It is a 0 (LOW) during horizontal and vertical sync tips. It is
a 1 (HIGH) at all other times.
These register bits may be read at any time over either the
serial or parallel control port. Since they are dynamic, their
states will change as appropriate during a parallel port read.
In fact, if the parallel control port is commanded to read reg-
ister 0E continually, the pins associated with these bits
behave as burst ag and composite sync timing outputs.
In serial control mode, these same data output pins (D1-0)
always act as a burst ag and composite sync TTL outputs,
the conditions of the serial control notwithstanding. The
states of the ags may be read over the serial port, but due to
the low frequency of the serial interface, it may be difcult to
get meaningful information.
Pixel Interface
The TMC2490(1)A interfaces with an 8-bit 13.5 Mpps (27
MHz) video datastream. It will automatically synchronize
with embedded Timing Reference Signals, per CCIR-656.
It also includes a master sync generator on-chip, which can
produce timing reference outputs.
CCIR-656 Mode
When operating in CCIR-656 Mode (MASTER = 0), the
TMC2490(1)A identies the SAV and EAV 4-byte code-
words embedded in the video datastream to derive all timing.
Both SAV and EAV are required.
MASTER Mode
When in MASTER Mode (MASTER = 1), the Encoder
produces its own timing, and provides HSYNC, VSYNC (or
B/T), SELC, and PDC (or CBSEL) to the Pixel Data Source.
SELC Output
The SELC output toggles at 13.5 MHz (1/2 the pixel rate),
providing a phase reference for the multiplexed luma/chroma
CCIR-656 datastream. It is HIGH during the rising edge of
the clock intended to load chroma data. This is useful when
interfacing with a 16-bit data source, and can drive a Y/C
multiplexer.
CBSEL Output
The CBSEL output identies the CB element of the CB-Y-
CR-Y CCIR-656 data sequence. It is HIGH during the rising
edge of the clock to load CB data. This will prevent uninten-
tionally swapping the CB and CR color components when
operating in MASTER mode and reading data from a
framestore.
PDC Output
The PDC output is a blanking signal, indicating when the
encoder expected to receive pixel data. When PDC is HIGH,
the incoming PD is encoded.
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