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參數(shù)資料
| 型號： | TMC2491AR2C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大小： | 208K |
| 代理商： | TMC2491AR2C |
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PRODUCT SPECIFICATION
TMC2490A/TMC2491A
3
Pin Assignments
Pin Descriptions
Pin Name
Pin Number
Value
Pin Function Description
Clock
PXCK
25
TTL
Pixel Clock Input. This 27.0 MHz clock is internally divided by 2
to generate the internal pixel clock. PXCK drives the entire
TMC2490(1)A, except the asynchronous microprocessor
interface. All internal registers are strobed on the rising edge of
PXCK.
Data Input Port
PD7-0
38–44, 3
TTL
Pixel Data Inputs. Video data enters the TMC2490(1)A on
PD7-0 (Figure 1).
Microprocessor Interface
D7-0
9–12, 14–17
TTL
Data I/O, General Purpose I/O, Chroma Input Port. When SER
is HIGH, all control parameters are loaded into and read back
over this 8-bit port. When SER = LOW, D0 can serve as a
composite sync output, D1 outputs a burst flag during the back
porch, D2-5 are General Purpose Outputs, and D6-7 are General
Purpose Inputs.
RESET
22
TTL
Master Reset Input. Bringing RESET LOW forces the internal
state machines to their starting states and disables all outputs.
SA1
4
TTL
Serial/Parallel Port Select. When SER is LOW, SA1 in
conjunction with SA0 selects one of four addresses for the
TMC2490(1)A.
SA0, ADR
5
TTL
Serial/Parallel Port Select. When SER is LOW, SA0 in
conjunction with SA1 selects one-of-four addresses for the
TMC2490(1)A. When SER is HIGH, this control governs whether
the parallel microprocessor interface selects a table address or
reads/writes table contents.
65-2490(1)A-02
SCL/
CS
SER
D7
D6
D5
D4
GND
D3
D2
D1
D0
PD6
PD7
VDD
GND
CHROMA
VDDA
CBYP
LUMA
GND
COMPOSITE
GND
SDA/R/
W
SA
0
/ADR
SA
1
PD
0
GND
V
DD
PD
1
PD
2
PD
3
PD
4
PD
5
HSYNC
VSYNC
,T/
B
CBSEL
,PDC
SELC
RESET
V
DD
GND
PXCK
V
DD
V
REF
R
REF
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
TMC2490A
TMC2491A
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