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參數資料
| 型號： | TMC2491AR2C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 36/36頁 |
| 文件大小： | 208K |
| 代理商： | TMC2491AR2C |
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PRODUCT SPECIFICATION
TMC2490A/TMC2491A
9
Control Register Denitions (continued)
General Control Register (0F)
7
6
5
4
3
2
1
0
PED21
Reserved
VSEL
CBSEL
VBIEN
Reserved
Reg
Bit
Name
Description
0F
7
PED21
VBI Pedestal Enable. When HIGH and FORMAT is 00 (NTSC) or 10
(PAL-M), pedestal is added to lines 21, 22, 283, 284, 285. When LOW, no
pedestal is placed on these lines. PED21 is valid for NTSC and PAL-M only
and should be LOW for all other formats.
0F
6
Reserved
Program HIGH.
0F
5
VSEL
Vertical Sync Select. When LOW, the TMC2490(1)A outputs a traditional
vertical sync on VSYNC. When HIGH, the chip outputs odd/even field
identification on the VSYNC pin, with 0 denoting an odd field.
0F
4
CBSEL
CBSEL/PDC pin function. When CBSEL = 0, the PDC signal is produced
on the CBSEL/PCD pin. When CBSEL = 1, the CBSEL signal is produced
on the CBSEL/PDC pin.
0F
3
VBIEN
VBI Pixel Data Enable. When VBIEN = 0, the vertical interval lines are
blanked. When VBIEN = 1, Pixel data is encoded into the VBI lines.
0F
2
Reserved
Program LOW.
0F
1–0
HDEL
Sync Delay. HDEL shifts the falling edge of the H and V syncs relative to the
PD port.
HDEL Result
00
H and V syncs are aligned with luminance pixel 735 (Y735)
01
H and V syncs are aligned with Blue color difference pixel 735
(Cb736)
10
H and V syncs are aligned with luminance pixel 736 (Y736)
11
H and V syncs are aligned with Red color difference pixel 735
(Cr736)
Refer to Figure 2a, HDEL Timing
Reserved Registers (10–1F)
7
6
5
4
3
2
1
0
Reserved
Reg
Bit
Name
Description
10–
1F
7–0
Reserved
May be left unprogrammed
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