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SYNCHRONIZATION
POWERGOOD OPERATION
PRE-BIASED OUTPUTS
OUTPUT RIPPLE CONSIDERATION
SLUS617B – APRIL 2005 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
The SYNC pin accepts logic level signals and is used to synchronize the TPS40074 to an external clock source.
Synchronization occurs on the rising edge of the signal at the SYNC pin. There is a fixed delay of approximately
300 ns from the rising edge of the waveform at SYNC to the HDRV output turning on the high-side FET. The pin
may be left floating in this function is not used, or it may be connected to GND. The frequency of the external
clock must be greater than the free running frequency of the device as set by the resistor on the RT pin (RRT).
This pin requires a totem pole drive, or open collector/drain if pull up resistor to either LVBP or a separate supply
between 2.5 V and 5 V is used. Synchronization does not affect the modulator gain due to the voltage feed
forward circuitry. The programmable UVLO thresholds are affected by synchronization. The thresholds are
shifted by the ratio of the sync frequency to the free running frequency of the converter. For example,
synchronizing to a frequency 20% higher than the free running frequency results in the programmable UVLO
thresholds shifting up 20% from their calculated free run values. The synchronization frequency should be kept
less than 1.5 times the free run frequency for best performance, although higher multiples can be used.
The PGD pin is an open drain output that actively pulls to GND if any of the following conditions are met
(assuming that the input voltage is above 4.5 V)
Soft-start is active (V
VSS < 3.5 V)
V
FB < 0.63 V
V
FB > 0.77 V
Programmable UVLO condition not satisfied (V
IN below programmed level)
Overcurrent condition exists
Die temperature is greater than 165
°C
Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the
output. Since synchronous buck converters inherently sink current some method of overcoming this
characteristic must be employed. Applications that require this operation are typically power rails for a multi
supply processor or ASIC. The method used in this controller, is to not allow the low side or rectifier FET to turn
on until there the output voltage commanded by the start up ramp is higher than the pre-existing output voltage.
This is detected by monitoring the internal pulse width modulator (PWM) for its first output pulse. Since this
controller uses a closed loop startup, the first output pulse from the PWM does not occur until the output voltage
is commanded to be higher than the pre-existing voltage. This effectively limits the controller to sourcing current
only during the startup sequence.
If the pre-existing voltage is higher that the intended regulation point for the output of the converter, the
converter starts and sinks current when the soft-start time has completed
In addition to the typical output ripple associated with switching converters, (which can vary from 5 mV to
150 mV) the TPS40074 exhibits a low-frequency ripple from 5 mV to 50 mV. The ripple, a consequence of the
charge pump in the driver supply regulator, is well bounded under changes in line, load, and temperature. The
ripple frequency does vary with the converter switching frequency and can vary from 10 kHz to 60 kHz.
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