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參數資料
| 型號： | TPS40074RHLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | GREEN, PLASTIC, QFN-20 |
| 文件頁數： | 2/41頁 |
| 文件大小： | 765K |
| 代理商： | TPS40074RHLT |
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VDD Input Voltage V
f O
S
C
Frequency
kHz
2
6
18
26
30
10
500
495
505
520
510
515
490
485
480
14
22
TYPICAL SWITCHING FREQUENCY
vs
INPUT VOLTAGE
fSW Switching Frequency kHz
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
0
100
0
200
400
600
800
1000
200
300
400
500
600
R
T
T
iming
Resistance
k
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO FUNCTION
R
KFF + 0.131
R
T
V
UVLO(on) * 1.61
10*3
V
UVLO(on)
2
) 1.886
V
UVLO * 1.363 * 0.02
R
T * 4.87
10*5
R2
T
SLUS617B – APRIL 2005 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Figure 3.
Figure 4.
The ramp generator circuit provides the actual ramp used by the PWM comparator and provides voltage
feed-forward by varying the PWM ramp slope as the line voltage changes. As the input voltage to the converter
increases, the slope of the PWM ramp increase by a proportionate amount. The programmable UVLO circuit
works by monitoring the level reached by the PWM ramp during a clock cycle. The PWM ramp must reach
approximately 1 V in amplitude during a clock cycle, or the converter is not be allowed to start. This
programmable UVLO point is set via a single resistor (RKFF) connected from KFF to VDD. RKFF , VSTART and RRT
are related by (approximately)
(4)
where
V
UVLO(on) is in volts
R
KFF and RT are in k
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary
up ±15% from this number. Figure 5 through Figure 7 show the typical relationship of VUVLO(on), VUVLO(off) and
RKFF at three common frequencies.
10
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