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參數資料
| 型號： | TPS40074RHLT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | GREEN, PLASTIC, QFN-20 |
| 文件頁數： | 38/41頁 |
| 文件大小： | 765K |
| 代理商： | TPS40074RHLT |
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SLUS617B – APRIL 2005 – REVISED OCTOBER 2006
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW node
voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal
BOOST
11
I
bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is
the available drive voltage for the high-side FET.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
COMP
6
O
FB pin to compensate the overall loop. This pin is internally clamped to a 3.4-V maximum output drive capability
for quicker recovery from a saturated feedback loop situation.
8-V regulator output used for the gate drive of the N-channel synchronous rectifier and as the supply for charging
DBP
9
O
the bootstrap capacitor. This pin should be bypassed to ground with a 1.0-F ceramic capacitor.
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
FB
5
I
voltage, 0.7 V.
GND
3
-
Ground reference for the device.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
HDRV
12
O
(MOSFET off).
Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink
from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The
voltage on this pin is compared to the voltage drop (VVDD -VSW) across the high side N-channel MOSFET during
ILIM
14
I
conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VVDD/2 and released
when SW is within 2 V of VVDD or after a timeout (the precondition time) - whichever occurs first. Placing a
capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,
effectively programming the ILIM blanking time. See Applications Information section.
A resistor is connected from this pin to VDD programs the amount of input voltage feed-forward. The current fed
KFF
15
I
into this pin is used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at
this pin is maintained at 400 mV.
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to PGND (MOSFET
LDRV
8
O
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.
4.2-V reference used for internal device logic and analog functions. This pin should be bypassed to GND with a
LVBP
17
O
0.1-F ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied.
This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10%
PGD
18
O
band around the 700 mV reference voltage.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of
PGND
7
the lower MOSFET(s).
RT
16
I
A resistor is connected from this pin to GND to set the switching frequency.
SA+
20
I
Noninverting input of the remote voltage sense amplifier.
SA-
1
I
Inverting input of the remote voltage sense amplifier.
SAO
2
O
Output of the remote voltage sense amplifier.
Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The
capacitor is charged with an internal current source of 12 A. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V
SS
4
I
less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on
the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is below
the internal offset voltage of 1 V (300 mV minimum ensured), the resulting output voltage is zero. Also provides
timing for fault recovery attempts. Maximum recommended capacitor is 22nF.
This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate drive
SW
10
I
timing. This pin is also the return path from the high-side FET for the floating high-side FET driver. A 1.5-
resistor is required in series with this pin to protect against substrate current issues.
SYNC
19
I
Logic input for pulse train to synchronize oscillator.
VDD
13
I
Supply voltage for the device.
6
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