
TPS65950
Integrated Power Management/Audio Codec
SWCS032 – OCTOBER 2008
www.ti.com
List of Figures
1-1
TPS65950 Block Diagram
.......................................................................................................
162-1
PBGA Bottom View
...............................................................................................................
174-1
Power Provider Block Diagram
..................................................................................................
364-2
VDD1 Dc-dc Regulator Efficiency
...............................................................................................
394-3
VDD1 Dc-dc Application Schematic
............................................................................................
404-4
VDD2 Dc-dc Regulator Efficiency
...............................................................................................
424-5
VDD2 Dc-dc Application Schematic
............................................................................................
434-6
VIO Dc-dc Regulator Efficiency in Active Mode
...............................................................................
454-7
VIO Dc-dc Application Schematic
...............................................................................................
464-8
Timings Before Sequence Start
................................................................................................
604-9
Timings—OMAP2 Power-On Sequence
.......................................................................................
614-10
Timings—OMAP3 Power-On Sequence
.......................................................................................
624-11
Power-Off Sequence in Master Modes
.........................................................................................
636-1
Audio/Voice Module Block Diagram
............................................................................................
656-2
Earphone Amplifier
................................................................................................................
666-3
Earphone Speaker
................................................................................................................
676-4
8-
Stereo Hands-Free Amplifiers.............................................................................................. 67 6-5
8-
Stereo Hands-Free .......................................................................................................... 69 6-6
Headset Amplifier
.................................................................................................................
696-7
Headset 4-Wire Stereo Jack Without an External FET
......................................................................
716-8
Headset 4-Wire Stereo Jack With an External FET
..........................................................................
726-9
Headset 5-Wire Stereo Jack
.....................................................................................................
736-10
Headset 4-Wire Stereo Jack Optimized
........................................................................................
746-11
Headset Pop-Noise Cancellation Diagram
....................................................................................
756-12
Predriver for External Class D
...................................................................................................
776-13
Vibrator H-Bridge
..................................................................................................................
786-14
Carkit Output Downlink Path Characteristics
..................................................................................
786-15
Digital Audio Filter Downlink Path Characteristics
............................................................................
796-16
Digital Voice Filter Downlink Path Characteristics
............................................................................
806-17
Voice Downlink Frequency Response With FS = 8 kHz...................................................................... 80 6-18
Voice Downlink Frequency Response With FS = 16 kHz .................................................................... 81 6-19
Analog and Digital Microphone Multiplexing
...................................................................................
846-20
Analog Microphone Pseudodifferential
.........................................................................................
866-21
Analog Microphone Differential
..................................................................................................
876-22
Digital Microphone Bias Module Block Diagram
..............................................................................
886-23
Digital Microphone Bias Module Timing Diagram
.............................................................................
896-24
Silicon Microphone Module
......................................................................................................
906-25
Audio Auxiliary Input
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916-26
Example of PDM Interface Circuitry
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92List of Figures
6