
TPS65950
Integrated Power Management/Audio Codec
www.ti.com
SWCS032 – OCTOBER 2008
6-27
Uplink Amplifier
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926-28
Carkit Input Uplink Path Characteristics
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936-29
Digital Audio Filter Uplink Path Characteristics
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946-30
Digital Audio Filter Uplink Path Characteristics
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956-31
Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 0 to 600 Hz) .................................. 95 6-32
Voice Uplink Frequency Response With FS = 8 kHz (Frequency Range 3000 to 3600 Hz) ............................ 96 6-33
Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 0 to 600 Hz)................................. 97 6-34
Voice Uplink Frequency Response With FS = 16 kHz (Frequency Range 6200 to 7000 Hz)........................... 97 7-1
USB 2.0 PHY Overview
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997-2
USB System Application Schematic
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1017-3
MCPC UART and Handshake Mode Data Flow
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1027-4
MCPC UART and Handshake Mode Timings
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1037-5
USB-CEA Carkit UART Data Flow
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1047-6
USB-CEA Carkit UART Timing Parameters
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1057-7
HS USB Interface—Transmit and Receive Modes (ULPI 8-Bit)
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1058-1
Typical Application Schematics
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1168-2
Typical Application Schematic (In-Rush Current Limitation)
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1178-3
Typical Application Schematic (BCI Not Used)
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1188-4
Automatic Charge Sequence Timing Diagram
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1259-1
Conversion Sequence General Timing Diagram
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12910-1
LED Driver Block Diagram
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13011-1
Keyboard Connection
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13112-1
Clock Overview
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13212-2
HFCLKIN Clock Distribution
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13312-3
Example of Wired-OR Clock Request
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13412-4
HFCLKIN Squared Input Clock
................................................................................................
13512-5
32-kHz Oscillator Block Diagram In Master Mode With Crystal
...........................................................
13612-6
32-kHz Crystal Input
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13712-7
32-kHz Oscillator Block Diagram Without Crystal Option 1
................................................................
13812-8
32-kHz Oscillator Block Diagram Without Crystal Option 2
................................................................
13912-9
32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3
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13912-10
32-kHz Square- or Sine-Wave Input Clock
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14012-11
32.768-kHz Clock Output Block Diagram
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14112-12
32KCLKOUT Output Clock
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14212-13
HFCLKOUT Output Clock
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14212-14
32KCLKOUT and HFCLKOUT Clock Stabilization Time
...................................................................
14312-15
HFCLKOUT Behavior
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14313-1
I
2C Interface—Transmit and Receive in Slave Mode
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14513-2
I2S Interface—I2S Master Mode
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14713-3
I2S Interface—I2S Slave Mode
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14713-4
TDM Interface—TDM Master Mode
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148List of Figures
7