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參數資料
型號: TPS65950ZXNR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝: 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數: 53/167頁
文件大小: 2566K
代理商: TPS65950ZXNR
13.4 Audio Interface: TDM/I2S Protocol
13.4.1 I2S Right- and Left-Justified Data Format
TPS65950
Integrated Power Management/Audio Codec
SWCS032 – OCTOBER 2008
www.ti.com
Table 13-3. I2C Interface Timing Requirements (continued)
Notation
Parameter
Min(3)
Max(4)
Unit
Slave Standard Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
250
ns
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
4.7
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
4
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
4
ns
Table 13-4. I2C Interface Switching Requirements(1)(2)
Notation
Parameter
Min(3)
Max(4)
Unit
Slave HS Mode
I1
tw(SCLL)
Pulse duration, SCL low
160
ns
I2
tw(SCLH)
Pulse duration, SCL high
60
ns
Slave Fast-Speed Mode
I1
tw(SCLL)
Pulse duration, SCL low
1.3
ns
I2
tw(SCLH)
Pulse duration, SCL high
0.6
ns
Slave Standard Mode
I1
tw(SCLL)
Pulse duration, SCL low
4.7
ns
I2
tw(SCLH)
Pulse duration, SCL high
4
ns
(1)
The capacitive load is:
100 pF in HS mode (3.4 Mbps)
400 pF in fast-speed mode (400 Kbps)
400 pF in standard mode (100 Kbps)
(2)
SDA equals I2C.SR.SDA or I2C.CNTL.SDA
SCL equals I2C.SR.SCL or I2C.CNTL.SCL
(3)
Min = Minimum value
(4)
Max = Maximum value
The TPS65950 acts as a master for the TDM and I2S interface or as a slave only for the I2S interface. If
the TPS65950 is the master, it must provide frame synchronization (TDM/I2S_SYNC) and bit clock
(TDM/I2S_CLK) to the host processor. If the TPS65950 is the slave, it receives frame synchronization and
bit clock.
The TPS65950 supports the I2S, TDM, left-justified, and right-justified data formats, but does not support
TDM slave mode.
Table 13-5 and Table 13-6 assume testing over the recommended operating conditions (see Figure 13-2
146
Timing Requirements and Switching Characteristics
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