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參數資料
型號： TPS65950ZXNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝： 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數： 52/167頁
文件大小： 2566K
代理商： TPS65950ZXNR
13.3 I
2C Timing
I2C.SCL
I2C.SDA
1
8
9
1
8
9
MSB
LSB
ACK
MSB
LSB
ACK
I1
I2
I3
I4
I7
I8
I9
Start
Restart
Stop
032-077
TPS65950
Integrated Power Management/Audio Codec
www.ti.com
SWCS032 – OCTOBER 2008
Table 13-2. TPS65950 Interface Target Frequencies (continued)
Target Frequency
I/O Interface
Interface Designation
1.5 V
Inter-IC sound (I2S)
1/(64 * Fs)(1)
Right-justified
1/(64 * Fs)(1)
TDM/I2S
Left-justified
1/(64 * Fs)(1)
TDM
1/(128 * Fs)(1)
Voice/Bluetooth PCM interface
PCM
1/(65 * Fs)(2)
(1)
Fs = 8 to 48 kHz; 96 kHz for RX path only (TDM/I2S interface)
(2)
Fs = 8 or 16 kHz (voice/Bluetooth PCM interface)
The TPS65950 provides two I2C HS slave interfaces (one for GP and one for SmartReflex). These
interfaces support the standard mode (100 kbps), fast mode (400 kbps), and HS mode (3.4 Mbps). The
GP I2C module embeds four slave hard-coded addresses (ID1 = 48h, ID2 = 49h, ID3 = 4Ah, and ID4 =
4Bh). The SmartReflex I2C module uses one slave hard-coded address (ID5). Master mode is not
supported.
Table 13-3 and Table 13-4 assume testing over the recommended operating conditions (see Figure 13-1).
Figure 13-1. I2C Interface—Transmit and Receive in Slave Mode
Table 13-3. I2C Interface Timing Requirements(1)(2)
Notation
Parameter
Min(3)
Max(4)
Unit
Slave HS Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
10
ns
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
70
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
160
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
160
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
160
ns
Slave Fast-Speed Mode
I3
tsu(SDA-SCLH)
Setup time, SDA valid to SCL high
100
ns
I4
th(SCLL-SDA)
Hold time, SDA valid from SCL low
0
0.9
ns
I7
tsu(SCLH-SDAL)
Setup time, SCL high to SDA low
0.6
ns
I8
th(SDAL-SCLL)
Hold time, SCL low from SDA low
0.6
ns
I9
tsu(SDAH-SCLH)
Setup time, SDA high to SCL high
0.6
ns
(1)
The input timing requirements are given by considering a rising or falling time of:
80 ns in HS mode (3.4 Mbps)
300 ns in fast-speed mode (400 Kbps)
1000 ns in standard mode (100 Kbps)
(2)
SDA equals I2C.SR.SDA or I2C.CNTL.SDA
SCL equals I2C.SR.SCL or I2C.CNTL.SCL
(3)
Min = Minimum value
(4)
Min = Minimum value
Timing Requirements and Switching Characteristics
145
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