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參數資料
| 型號： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收發器 |
| 文件頁數： | 12/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14C01MHV |
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2
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2
2.3.1
Link/PHY Interface
Four operations may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data
receive. The LLC issues a link service request to read or write a PHY register, or to request that the PHY gain control
of the serial-bus to transmit a packet. (refer to Section 5).
2.3.2
Arbitration Control
Controls the arbitrating sequence that the TSB14AA1A uses to arbitrate the bus between competing nodes (refer to
Section 6).
2.3.3
Data Resync/Decode
During packet reception, the data information is received on RDATA and strobe information is received on RSTRB.
The received data and strobe information is decoded to recover the received clock signal and the serial data bits,
which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent
to the associated LLC.
2.3.4
Data/Arb Encode
During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched
internally (in the TSB14AA1A) in synchronization with the system clock. These bits are combined serially, encoded,
and transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is
transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB.
2.3.5
CFRs
The configuration registers (CFRs) control the operation of the TSB14AA1A. The register definitions are specified
in Section 3.
2.3.6
Clock Generation
Provides system clock signals used to control transmission of the outbound encoded strobe and data information,
synchronization of the LLC and PHY, and is used for resynchronization of the received data.
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