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參數資料
| 型號： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收發器 |
| 文件頁數： | 26/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14C01MHV |
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6
–
6
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY Cti [0:1]
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY D [0:7]
00
ZZ
ZZ
ZZ
01
01
10
10
10
10
00
00
ZZ
Link Cti [0:1]
ZZ
ZZ
00
00
D0
D1
D2
Dn
00
00
ZZ
Link D [0:7]
ZZ
Single Packet
ZZ
ZZ
ZZ
ZZ
00
11
00
ZZ
00
ZZ
ZZ
ZZ
PHY Cti [0:1]
ZZ
ZZ
ZZ
00
00
00
ZZ
00
ZZ
ZZ
ZZ
PHY D [0:7]
ZZ
10
10
01
00
ZZ
ZZ
ZZ
01
ZZ
01
10
10
Link Cti [0:1]
Dn-1
00
00
ZZ
ZZ
ZZ
00
ZZ
00
D0
D1
Link D [0:7]
Dn
Continued Packet
ZZ = High- Impedance State
D0 = > Dn = Packet Data
Figure 6
–
4. Transmit Timing
6.1.5
Receive
When data is received by the PHY from the serial bus, it transfers the data to the link for further processing. The PHY
asserts receive (see Table 6
–
1) on the CTL lines and asserts each D terminal high. The PHY indicates the start of
the packet by placing the speed code on the data bus. The PHY then proceeds with the transmission of the packet
to the link on the D lines while keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the PHY asserts idle on the CTL terminals, which completes the receive operation (see Figure 6
–
5).
NOTE:
The speed code is a PHY-link protocol and is not included in the CRC.
PHY
Ctl[0:1]
PHY
D[0:1]
00
10
10
10
10
10
10
00
00
00
11
11
SPD
D0
D1
Dn
00
00
NOTE A: SPD = Speed Code (for the backplane, this speed is fixed at D0, D1 = 00)
D0 to Dn = Packet data
Figure 6
–
5. Receive Timing
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