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參數資料
| 型號： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收發器 |
| 文件頁數： | 13/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14C01MHV |
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3
–
1
3 Internal Register Configuration
There are 10 accessible internal registers in the TSB14AA1A. The configuration of the registers is shown in Table
3
–
1, and corresponding field descriptions given in Table 3
–
2.
A reserved register or register field (marked as reserved or RSVD in the following register configuration tables) is read
as 0, but is subject to future usage.
Table 3
–
1. Base Register Configuration
Address
BIT POSITION
3
0
1
2
4
5
6
7
0000
PHYSICAL_ID
R_F_TEST
0001
TD
IBR
RESERVED
0010
LAST_ARB_WON_PHYSICAL_ID
RSVD
E
0011
RDATA
RSTRB
XFR_SPD
E_REGISTER_COUNT
0100
PRIORITY
RESERVED
0101
PRODUCT IDENTIFIER
RESERVED FOR TEST
0110
EBLREQ
IRBR
SMRST
SWHRST
LAST_ARB_WON_PRIORITY
0111
DDLS
DSLS
ENDLS
RESERVED
TDATA
TSTRB
TDOE
OCDOE
1000
RESERVED FOR TEST
1001
RESERVED FOR TEST
Table 3
–
2. Base Register Field Description
FIELD
SIZE
TYPE
DESCRIPTION
RESERVED
R/W
All fields marked as reserved or RSVD must be read as 0. Whenever software is
developed that writes to a register that has a reserved field, software must write a 0 to
each reserved bit. In this way a bit can be added later with the default value of 0 that
reverts to previous functionality. Whenever a read is done of a register that has
reserved fields, software must not depend on the reserved fields to hold any particular
value.
RESERVED FOR TEST
Reserved
for Test
All fields marked as reserved for test or R_F_TEST may only be written to as a test to
allow reading of and writing to the entire 8 bits of a register. For normal operation of the
PHY the bit(s) should be set to 0. Whenever a read is done of a register that has
reserved for test fields, software must not depend on the reserved for test fields to hold
any particular value.
PHYSICAL_ID
6
R/W
Physical layer ID for this node. Unlike the equivalent field in the cable environment, the
physical ID in the backplane environment is writeable. The power-up state of this field is
000000b. The hardware-reset state of this field is the binary state of the external ID pins
on the device. This field is unaffected by bus reset (IBR, IRBR) and state machine reset
(SMRST). It is reinitialized to the external pin values by a hardware reset or reset
initiated by writing to the software initiated hard reset (SWHRST) bit.
TD
1
R/W
Transceiver disable. When set to 1 the PHY sets the output enable signals so that the
bus transceivers are disabled. The TSB14AA1A ignores any link layer service actions
that require a change to this bus output state. The power-up state of this field is 0. The
state of this bit is not affected by bus resets.
IBR
1
R/W
Initiate bus-reset. When set to 1, the PHY initiates a bus request immediately (without
arbitration). This bit causes assertion of the reset signal for approximately 8
μ
s and is
self-clearing. The IBR bit may be used to initiate bus resets when open collector
transceivers are implemented. In general the IRBR bit must be used to initiate bus
resets instead of IBR. The IBR bit is retained for software compatibility with the
TSB14CO1A when used with open-collector transceivers. When 3-state transceivers
are implemented, the IRBR bit must be used to initiate bus resets. The power-up state
of this field is 0.
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