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參數資料
| 型號： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收發器 |
| 文件頁數： | 34/35頁 |
| 文件大小： | 224K |
| 代理商： | TSB14C01MHV |
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6
–
14
6.5.2
Bus Reset
Once a PHY control request of Bus_Reset is communicated from the node controller to the PHY the PHY
communicates a Bus_Reset onto the bus.
NOTE:
Since a PHY transmitting a Bus_Reset must also react accordingly once the Bus_Reset
event is detected, its state machines do have the opportunity to advance beyond those of other
nodes. This ensures that all nodes are in a somewhat similar state after such a Bus_Reset
event.
Once a PHY detects that a Bus_Reset event has occurred on the bus, it communicates a bus reset status to the LLC.
The node controller initializes a bus reset by writing to the PHY control register with the IBR bit or IRBR bit set to 1.
The PHY hardware resets the IBR and IRBR bit to zero on detection of its own bus reset.
6.6
Live Insertion
It is up to the user to design the node or module to safely receive power from the particular backplane they are using
during a live insertion. But in principle, live insertion is supported and does not cause a bus reset event to occur.
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