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| 型號： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收發器 |
| 文件頁數： | 31/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14C01MHV |
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6
–
11
6.3.3
Arbitration Sequence Format
The following format for the arbitration sequence is used:
PRIORITY
ARBITRATION NUMBER
4-bits
6-bits
Each module on the backplane has unique 6-bit arbitration number that is equal to the nodes Physical_ID.
The arbitration number is preceded by four bits of priority. The MSB of the priority field is transmitted first.
The LSB of the priority field is followed by the MSB of the arbitration number.
Dynamic assignment of priority is accommodated.
The lowest priority level (all zeroes) is reserved for fair arbitration, and the highest priority level (all ones)
is reserved for the identification of the cycle start packet.
6.4
Arbitration
Unless a node is using immediate arbitration to access the bus (in which case there is no contention for the bus), it
is possible that more than one node can attempt to access the bus at a given time. Consequently, it is necessary for
a node to arbitrate for the bus in order to gain access to the bus.
NOTE:
A node uses immediate arbitration to send an acknowledge. Since there is no
contention for the bus in this case, arbitration is not necessary. A node that is transmitting an
acknowledge does not arbitrate for the bus, but merely waits for an acknowledge gap to be
detected before it begins transmission. If a node is attempting to gain access to the bus without
using immediate access, it must first arbitrate for the bus.
Arbitration occurs in response to a PHY arbitration request from the link. Nodes begin arbitrating once the bus has
become idle for a predetermined amount of time (the appropriate gap indication occurs). Once this happens, nodes
begin a bit-by-bit transmission of their arbitration sequence.
A node can obtain access to the bus in a limited number of ways. Since some arbitration classes allow nodes to begin
arbitration before others, nodes arbitrating with certain arbitration classes can detect that the bus is busy before they
can begin to arbitrate. In this way, certain arbitration classes can be bypassed, e.g., fair and urgent nodes do not get
a chance to arbitrate when another node is sending an acknowledge.
The backplane environment supports the fair, urgent, and immediate arbitration classes.
6.4.1
Fairness Intervals
The fairness protocol is based on the concept of a fairness interval. A fairness interval consists of one or more periods
of bus activity separated by short idle periods called subaction gaps and is followed by a longer idle period known
as an arbitration reset gap. At the end of each gap, bus arbitration is used to determine the next bus owner. This
concept is shown in Figure 6
–
9.
arb
data
a
a
arb
data
a
arb
a
arb
data
a
arb
Owner A
Owner B
Owner M
Fairness Interval N
Fairness
Interval N
–
1
Fairness
Interval N+1
Subaction Gaps
Arbitration
Reset Gap
Arbitration
Reset Gap
Subaction
Figure 6
–
9. Fairness Interval
The implementation of the fair arbitration protocol is defined in terms of these fairness intervals as is discussed in
the following paragraphs.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB2203X6MMX30M | IC APEX 20KE FPGA 200K 240-PQFP |
| TSB2204.5X12MMX20M | IC APEX 20KE FPGA 200K 240-PQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSB14C01PM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| TSB150002DS | 制造商:TE Connectivity 功能描述: |
| TSB150004DS | 制造商:TE Connectivity 功能描述:Conn Europa Terminal Blocks 8 POS 13.5mm Screw ST Cable Mount 40A/Contact |
| TSB150005 | 功能描述:柵欄接線端子 5P TERM BLOCK 13.5MM 300V 40A RoHS:否 制造商:TE Connectivity / AMP 產品:Barrier Terminal Blocks 系列: 類型:Dual Barrier, Flat Block without Mounting Ears 節距:9.53 mm 位置/觸點數量:2 線規量程:22-12 電流額定值:20 A 電壓額定值:300 V 安裝風格:Through Hole 安裝角:Vertical 端接類型:Screw 觸點電鍍:Tin |
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