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參數資料
| 型號： | TSC2008TRGVRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, PLASTIC, VQFN-16 |
| 文件頁數： | 13/35頁 |
| 文件大小： | 418K |
| 代理商： | TSC2008TRGVRQ1 |
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SBAS552
– JUNE 2011
DIGITAL INTERFACE
The TSC2008-Q1 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master
generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start
and synchronize transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the
slave SDI (MOSI
—master out, slave in) pin under the control of the master serial clock. As the byte shifts in on
the SDI (MOSI) pin, a byte shifts out on the SDO (MISO
—master in, slave out) pin to the master shift register.
The idle state of the TSC2008-Q1 serial clock is logic low, which corresponds to a clock polarity setting of 0
(typical microprocessor SPI control bit CPOL = 0). The TSC2008-Q1 interface is designed so that with a clock
phase bit setting of 0 (typical microprocessor SPI control bit CPHA = 0), the master begins driving its MOSI pin
and the slave begins driving its MISO pin half an SCLK before the first serial clock edge. The CS (SS, slave
select) pin can remain low between transmissions.
Table 1. Standard SPI Signal Names vs Common Serial Interface Signal Names
SPI SIGNAL NAMES
COMMON SERIAL INTERFACE NAMES
SS (Slave Select)
CS (Chip Select)
MISO (Master In Slave Out)
SDO (Serial Data Out)
MOSI (Master Out Slave In)
SDI (Serial Data In)
As a comparison to the popular TSC2046 timing characteristics, a few differences between the interfaces are
worth notice:
1. Unlike the TSC2046, there is not a 15 SCLK cycle for the TSC2008-Q1.
2. There is an adjusted SDO timing that allows an 8-bit, back-to-back cycle.
3. The TSC2008-Q1 uses an internal conversion clock; therefore, the SPI serial clock (SCLK) can only affect
the acquiring period and I/O transfer.
4. The TSC2008-Q1 uses an internal clock to perform the conversion. PENIRQ rises when the conversion is
complete. If the host issues an SCLK before the conversion is complete, PENIRQ also rises, but the
conversion result is invalid.
5. If a new command is issued before a conversion is complete (indicated by EOC), then the conversion is
aborted.
6. Releasing the SPI bus (by raising CS) during the conversion is OK, but releasing the SPI during the I/O
transfer (for example, read result) aborts the data transfer.
20
Copyright
2011, Texas Instruments Incorporated
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